The primary purpose of this work is to automate selection of key attributes of a test data compression environment such as Embedded Deterministic Test, the first commercial test compression product. Given a test compression setup, the main objective of the proposed approach is to quickly estimate the expected test pattern count, test data volume, and the resultant test application time within the framework of the actual test compression flow when using ATPG-produced test cubes. This way one can mimic a process of test cube merging and anticipate compressibility of the resultant test patterns without resorting to CPU-intensive ATPG runs and solvers of linear equations. The obtained results, reported herein, are compared with actual stuck-at fault test patterns generated by a commercial test compression tool for several industrial designs in order to validate the proposed model. This allows a final tuning of the new scheme to arrive with a fast and accurate test compression advisement method. It can be used, prior to further steps, to devise the key elements of a test compression ecosystem such as the number of input channels and the size of on-chip test data decompressor.

On-chip test data decompressors [ 1 ] are the very first devices that have had deployed ring generators [ 2 , 3 ] – high performance linear feedback shift registers (LFSRs) – that quickly proved themselves as versatile solutions capable of outperforming traditional schemes through an unmatched speed of operations and layout-friendly structures [ 4 ]. Given a characteristic (feedback) polynomial, ring generators feature smaller internal fan-outs, shorter propagation paths, and simpler circuit layout and routing than popular and commonly used Fibonacci or Galois LFSRs [ 5 , 6 ] whose long irregular feedback paths may limit the operating speed, cause frequency degradation, and may take up a fair amount of silicon area, especially for polynomials with a large number of terms [ 7 ]. Figure 1 recalls a basic architecture of a 32-bit ring generator with a primitive polynomial h ( x ) = x 32 + x 28 + x 23 + x 20 + x 17 + x 12 + x 8 + x 4 + 1, which causes this ring generator to go through all possible 2 32 – 1 nonzero values before returning to a seed state. Typically, its structure can be created by forming a ring counter, and then by adding feedback taps which correspond to successive terms of a characteristic polynomial. A feedback loop associated with tap x k is made up from k adjacent flip-flops, beginning with the leftmost ones, as shown in the figure. Note that two feedback nets cannot cross each other [ 2 ]. If one uses an appropriate characteristic polynomial, then a ring generator may assume a regular ladder-like structure. An extensive collection of such primitive polynomials is available in [ 8 ]. Since a subset of k adjacent flip-flops can be chosen in different ways as long as the resultant feedback line does not cross any other feedback line, the ring generators offer an appreciable degree of flexibility in shaping their structures.

Nonlinear feedback shift registers (NLFSRs) are well-positioned to play the key role in securing variety of digital ecosystems. They have already been deployed as major building blocks of several hardware stream ciphers, and are expected to become an essential part of hardware roots of trust that protect integrated circuits (ICs) against hardware security threats and mitigate risks associated with an unauthorized access and usage of ICs. In this article, we present two new sets of Galois NLFSRs with maximum and near maximum prime periods, respectively. All reported registers have been identified by virtue of an FPGA-based engine running in parallel around 8000 search processes. This article provides a detailed description of metrics used to characterize output sequences produced by NLFSRs, such as the number of n-tuples each output sequence is comprised of, linear complexity of output sequences, and the total number of different maximum-length sequences obtained by means of simple linear filters driven by the examined registers. This article is accompanied by tables listing all found and never presented before NLFSRs, altogether with their architectural details and the corresponding metrics.

With the biennial doubling of the number of transistors in a given area of silicon, contemporary integrated circuits (IC) are forging more and more often and will continue to forge complex system-on-chip (SoC) designs. Their equally complex manufacturing and in-system tests are now carried out through top-level test data delivery nets that enable fast streaming of test data to, from, and throughout a chip. However, it is essential to apply restrictions mitigating risks associated with unauthorized access and usage of SoCs as well as to protect the test infrastructure against hardware security threats, and thus to prevent leakage of secret information or other sensitive assets while tests are carried out. Existing security IP cores raise concerns related to their complexity in terms of area footprint, performance, power, impact on an SoC integration flow, and testability. This paper presents simple and lightweight, yet effective and scalable, test data stream ciphers (SCs) that can be used to encrypt and decrypt test data employed in tests of SoCs and delivered via Streaming Scan Network (SSN) – a new packetized test data network. A single cipher is comprised of three Galois nonlinear feedback shift registers working in tandem to yield a large number of parallel, cryptographically secure pseudorandom keystreams. A comprehensive evaluation, including NIST statistical test suits, show high efficiency of the proposed ciphers, and is reported herein.

Additive stream ciphers (SCs) play a host of roles in securing variety of digital ecosystems. In particular, they can encrypt and decrypt test data used in manufacturing and in-system tests of digital integrated circuits (ICs). In this capacity, SCs have become an essential part of instruments that protect ICs against hardware security threats and mitigate risks associated with an unauthorized access and usage of ICs, possibly due to scan chains. However, many IC vendors keep raising concerns attributable to the complexity of existing SCs in terms of area overhead, performance, impact on a design flow, and testability. Here is where this work comes in. It introduces a simple and lightweight, yet effective and scalable, test data stream cipher Lancet developed for the Streaming Scan Network (SSN) technology to decrypt and encrypt the content of the IJTAG communication and the SSN bus. It builds on a hybrid ring generator working in tandem with two nonlinear Galois feedback shift registers to yield a large number of parallel, cryptographically secure pseudorandom keystreams. A comprehensive evaluation, including NIST test suits, show the efficiency of the proposed cipher, and is reported herein.

Protection of integrated circuits (ICs) against hardware security threats has been tackled by many schemes proposed to mitigate risks associated with an unauthorized access and usage of ICs in general, and intellectual property (IP) cores in particular. Typically, this is accomplished by virtue of hardware roots of trust whose crucial security primitives entail cryptographic hash functions. They provide data integrity services and thus can support the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise concerns regarding the complexity of certain hash functions in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, lightweight, scalable cryptographic hash function H2B. It builds on a hybrid ring generator, i.e., an area and time-optimized version of a linearfeedback shift register, which works in tandem with a nonlinear sequential circuitry whose feedback network comprises bent-like functions. A comprehensive evaluation, including test suits from the National Institute of Standards and Technology, shows the feasibility and efficiency of the proposed scheme and is reported herein.

Ring generators are high speed devices formed by transformations that alter the structure of conventional linear feedback shift registers (LFSRs) while preserving a transition function of the original circuits [8]. They feature a reduced number of levels of XOR logic, minimized internal fan-outs, and simplified layout and routing. This paper discusses hybrid ring generators – a new class of lightweight linear finite state machines. While they use the principal design rules of conventional ring generators, the new devices can reduce the number of XOR gates up to seven times compared to conventional rings implementing the same characteristic polynomial. It makes a substantial contribution toward the performance of linear circuits used in a variety of test applications. Several issues related to hybrid ring generators such as designing MISRs, programable PRPGs, or phase shifters are also discussed in the paper along with data providing architectural details of hybrid ring generators for sizes up to 256 bits.

There are many schemes proposed to protect integrated circuits (ICs) against an unauthorized access and usage, or at least to mitigate security risks. They lay foundations for hardware roots of trust whose crucial security primitives are generators of truly random numbers. In particular, such generators are used to yield one-time challenges (nonces) supporting the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise several concerns regarding the complexity of these solutions, both in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, all-digital lightweight and self-testable random number generator to produce a nonce. It builds on a generic ring generator architecture, i.e., an area and time optimized version of a linear feedback shift register, driven by a multiple-output ring oscillator. A comprehensive evaluation, based on three statistical test suits from the National Institute of Standards and Technology and BSI, show feasibility and efficiency of the proposed scheme and are reported herein.

A hardware root of trust (RoT) is the foundation on which all secure operations of a circuit depend, including those related to DFT. Despite many countermeasures aimed at facing potential threats such as untrusted users accessing a test interface, IC vendors raise several concerns regarding the complexity of such solutions, both in terms of area overhead and the impact on the design flow. These concerns have motivated this work presenting a simple, yet effective, comprehensive and non-intrusive lightweight hardware root of trust to counteract scan-related security threats. It builds on and easily integrates with a Streaming Scan Network (SSN) technology and takes advantage of its inherent data scrambling and packetized test data distribution.

The semiconductor industry ramping up design capabilities for emerging technologies is facing unprecedented test quality and yield management challenges. To facilitate diagnosis of yield issues and to enable repair processes, an accurate defect isolation is needed with support of more advanced test, diagnostic, and yield analysis tools. Scan remains instrumental in developing more advanced DFT technologies, including logic BIST and on-chip test data compression. Its reliable operations are essential for test pattern bring-up, failure analysis, and yield learning. This paper demonstrates how to re-architect on-chip test data compression environment to enable multiple and repeated scan integrity tests for advanced test procedures, including various forms of stroboscopic electron-beam imaging and laser voltage imaging. The presented approach avoids the repetitive loading of scan chains and therefore reduces significantly test time and may support advanced diagnostic techniques. The new solution has virtually no area overhead, and does not compromise the performance of the original test logic.

The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.