Test set compaction is one of the key steps of the postproduction test known to bring down test pattern counts. This, in turn, allows one to reduce the corresponding test data volume, test application time, and hence the cost of testing. This article presents a method that strives to reduce the number of automatic test pattern generation (ATPG)-produced deterministic test patterns to deliver compact test sets. In principle, the new scheme works with a meaningful representation of test patterns by using external and internal necessary assignments (NAs) to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust satisfiability (SAT)-based ATPG that produces a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for 12 large industrial cores and stuck-at faults confirm superiority of the proposed scheme over the state-of-the-art test set compaction techniques and are reported herein.

Test compaction and the associated test data compression are two key components of the post-production test as they reduce test pattern counts, the resultant test data volume, test application time, and hence the cost of testing. The paper describes a method that strives to reduce the number of ATPG-produced deterministic test patterns to deliver compact test sets. In principle, it is based on a dimensionality reduction paradigm by working with a meaningful representation of test patterns using external and internal necessary assignments to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust SAT-based ATPG and its solvers producing a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for several industrial designs and stuck-at faults confirm superiority of the proposed scheme over state-of-the-art test set compaction techniques and are reported herein.

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This article presents maXpress-an X-tolerant tunable compactor deploying a new scan chain selection mechanism capable of completely masking X states, as required by many in-system or one-directional streaming test applications, within redefinable groups of scan chains and designated scan shift cycles. The proposed scheme is also supporting separate observation scan chains that, in contrast to conventional scan, capture faulty effects every shift cycle, while their content is gradually shifted into a compactor shared with the remaining chains. In addition to a new layout-friendly architecture, the article proposes algorithms to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

As cars become increasingly computerized and their safety functions evolve rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is rising dramatically with high-end models containing hundreds of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive systems. This article presents a scan-based test scheme optimizing test time and area overhead during manufacturing and in-system test of automotive electronics. The proposed scheme deploys observation test points that capture the faulty effects in every shift cycle into separate observation scan chains. To reduce area overhead, the scheme enables the sharing of flip-flops among control points. It is also shown how test points enhance test coverage (TC) in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine TC are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in test quality over traditional solutions.

There is a growing number of integrated circuits that deploy hybrid test schemes combining on-chip test compression with logic BIST, with both techniques working synergistically to deliver high quality tests. As their architectural differences are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This paper presents maXpress – an X-tolerant programmable compactor deploying a new scan chain selection mechanism capable of completely (as required by many in-system test applications) masking X states within redefinable groups of scan chains and designated scan shift cycles. In addition to the new architecture, the paper proposes an algorithm to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for a variety of industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

This article presents a next-generation test data compression scheme. It builds on the isometric compression paradigm, but makes it more flexible and elevates encoding efficiency to values unachievable through state-of-the-art sequential compression schemes. Furthermore, its programmable selection of full-toggle scan chains ensures high test coverage and virtually eliminates compression aborts. The presented approach follows from a fundamental observation that among test cube care bits, only a very few have a status of necessary assignments (their locations cannot be changed), whereas the remaining ones have alternative sites. These test cubes are used to form circular test templates which synergistically control a decompressor and guide back ATPG to find assignments yielding highly compressible test patterns. A redesigned low-silicon-area decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. The experimental results obtained for large industrial designs and other benchmark circuits confirm the superiority of the proposed scheme over existing techniques and are reported herein.

As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimizing test time and area overhead during in-system test applications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops among control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in quality of test over traditional BIST schemes.

The paper presents a novel test data compression scheme. This low-silicon-area solution builds on the isometric compression paradigm, but makes it more flexible, elevates encoding efficiency to values unachievable through any conventional type of sequential compression, and ensures high test coverage due to programmable selection of full toggle scan chains. The presented approach follows from a fundamental observation that only a few specified positions in test cubes are necessary to detect faults, while the remaining ones have alternative sites. Such test cubes are used to form circular test templates which synergistically control a decompressor and guide ATPG to find assignments yielding highly compressible test cubes. A redesigned decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. Experimental results obtained for large industrial designs confirm superiority of the proposed scheme over state-of-the-art techniques and are reported herein.

This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes. Alternatively, one may consider applying a much larger number of vectors within the same time interval. Although the new scheme may resemble traditional BIST logic, it is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid test points that creates this new synergistic LBIST paradigm. The hybrid observation points, inserted at the most suitable locations, capture faulty effects every shift cycle into dedicated flip-flops that form separate scan chains. Their content is gradually shifted into a compactor, which is shared with the remaining scan chains that still deliver test responses captured once the entire test pattern has been shifted-in. Experimental results obtained for industrial designs illustrate feasibility of the proposed BIST scheme in terms of test time, test coverage, and area overhead, and they are reported herein.

This paper introduces a low-power test compression scheme that can also be used in a conventional BIST environment. The key contribution is an observation that simple broadcasting of a constant value to predetermined subsets of scan chains allows visible reductions of both toggling rates and pattern counts provided these subsets can be regrouped when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of the existing scan gating logic, its synergistic use with test compression algorithms yields a low scan load switching activity, reduced test time, and less intensive traffic of control data. Consequently, the proposed scheme helps to resolve problems related to test power dissipation and elevated test durations.