Demo Data from EDBT 2026 / reviewers in the wild / expert
Hans Grobler
dblp:156/1698
· DBLP profile ↗
3ranked-venue papers
0as first author
2since 2021 · last 2025
0000-0002-1343-0515ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 2 · 2 since 2021Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 46% Processor architecture and microarchitecture · 30% Reconfigurable computing and FPGAs · 23% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
dataflow architecture |
0.2 | 1 | 2015 | Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Hardware accelerators and domain-specific architectures › signal processing accelerator
radar signal processing |
0.2 | 1 | 2015 | Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Hardware accelerators and domain-specific architectures
signal processing accelerator |
0.2 | 1 | 2015 | Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Reconfigurable computing and FPGAs › FPGA-based processor implementation
soft-core processor |
0.2 | 1 | 2015 | Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Processor architecture and microarchitecture
instruction-level parallelism |
0.1 | 1 | 2015 | Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Methods — techniques the papers use, named apart from their topics
software pipelining · 0.2iterative design methodology · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | FPEVO: Fused point-edge visual odometry for low-structured and low-textured scenesabstractVisual odometry is an essential component of vision-based robotic navigation systems. A primary limitation of existing visual odometry solutions is their inability to achieve satisfactory performance in both high- and low-textured regions. In this paper, a robust RGB-D visual odometry method is proposed that fuses point and edge features. By combining the descriptiveness of feature points with the structure provided by edge data, a method that is robust to low-textured scenes is developed. Edge features are first detected and grouped based on the Gestalt principles of continuity and proximity. Edge groups are then associated between the current and previous frames using point features in the vicinity of the edges. Pose estimation is thereafter performed by first matching points between associated edge groups, filtering these points based on structural constraints imposed by the edges, and estimating the motion of the agent. Compared to state-of-the-art alternatives, such as REVO, MSC-VO, DROID-VO and SplaTAM on the TUM RGB-D, ICL-NUIM and Tartan-Air datasets, the resulting method reduces the root mean square absolute trajectory error, and translational and rotational relative pose errors by up to 58%, 75%, and 82%, respectively. This indicates that our method is not only more accurate than current approaches, but also more consistent, especially in low-structured and low-textured environments. • A method by which edge pixels can be grouped and matched between frames. • Localization by fusing the structure of edges with point feature descriptiveness. • Robust pose estimation in low-textured and low-structured environments. • Improved pose estimation accuracy compared to state-of-the-art alternatives. Dylan Brown, Hans Grobler, Johan Pieter de Villiers |
J. Vis. Commun. Image Represent. | 2 |
| 2024 | Adapting projection-based LiDAR semantic segmentation to natural domainsabstractIn this paper, an approach to the semantic segmentation of 3D LiDAR point clouds obtained from natural scenes is introduced. Using a state-of-the-art projection-based semantic segmentation model as the core segmentation network, several recent advances in projection-based 3D semantic segmentation methods are aggregated into a single model. These adaptions include: scan unfolding, soft-kNN post-processing, and multi-projection fusion. A novel Naïve Bayesian approach to multi-projection fusion which weights class probabilities based on the outputs of the base classifiers is proposed to further increase robustness. Quantitative and qualitative evaluations on several datasets, including scenes from both urban and natural environments; show that aggregating these adaptions into a single model can further improve the accuracy of state-of-the-art projection-based approaches. Finally, it is demonstrated that the novel Naïve Bayesian approach to multi-projection fusion addresses a number of the challenges inherent to natural data while also improving results on urban data. Kelian J. L. Massa, Hans Grobler |
J. Vis. Commun. Image Represent. | 2 |
| 2015 | Soft-Core Dataflow Processor Architecture Optimized for Radar Signal ProcessingabstractCurrent radar signal processors (RSPs) lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel soft-core streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction-level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end digital signal processor (DSP) processor by an average factor of 14 over a range of typical operating parameters in an RSP application. Rene Broich, Hans Grobler |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |