As design-for-manufacturability techniques have become widely used to improve the yield of nano-scale semiconductor technology in recent years, hotspot detection methods have been investigated with a view to calibrating layout patterns that tend to reduce yield. In this paper, we propose two graph models, i.e., skeleton graph and space graph, to formulate polygon topology and spatial relationship among polygons. In addition, a Prüfer encoding-based method is presented to encode each skeleton graph. Single polygon matching problem is then equivalent to the verification of graph isomorphism, which is realized by checking the identity of two enhanced Prüfer codes associated with two skeleton graphs. A branch and bound-based pattern anchoring algorithm is presented to resolve the vertex ordering problem for isomorphism checking. The general exact pattern matching problem can then be accomplished by adopting the space graph to identify the similarity of spatial relationship among polygons. Vias are one of the most device components that attract much attention in monitoring manufacturing variation due to via alignment issue, but hotspot detection rarely takes vias into consideration. Multilayer hotspot detection can also be realized by extending the skeleton graph to maintain the relations between adjacent layers through vias. Experimental results show that we can achieve 5.6 × runtime speedup than design-rule-based methodology in average for single layer hotspot detection while the runtime for multilayer hotspot is roughly equal to the summation of that for individual single layer hotspot detection.