This article presents Second-Order Sliding Mode Control (SOSMC) to synchronize the three-phase grid-tied inverter and discuss the existing problem in the synchronization process through conventional PLL schemes and so to eliminate the problems related to the PLL the proposed PLL-less strategy employ the Second-Order Sliding Mode Controller, the suggested controller is implemented in stationary reference frame (alpha-beta reference frame) to eliminate the need for PLL and since Park's transformation is also not required the computational burden is also reduced in this approach, further the proposed model is compared with the existing PLL-less strategy and the results shows the effectiveness of the proposed method in reducing the power ripples and keeping the system stable even in unbalanced conditions.

This paper deals with the phenomenon of the circulating current that propagates between the two H-Bridges via the ground, termed the circulating common-mode current (CCMC). The circumstances that facilitate the CCMC are presented with experimental validations. The propagation path and the voltage source of the CCMC are analyzed with the help of the commonmode (CM) equivalent circuit. In addition, the design of the coupled inductor to address the CCMC is discussed in detail. All the experimental validations are performed on a prototype DAB converter.

A simple and fast technique for the estimation of positive and negative sequence components under unbalanced grid conditions is proposed. Grid synchronization is achieved by the application of instantaneous symmetrical components method on stationary and orthogonal αβ reference frame. In this paper, the frequency dependent variable time-delay based algorithm is used to generate the quadrature signals used on αβ reference frame. The frequency adaptive characteristic of the time-delay method is achieved by SOGI-FLL (Second Order Generalized Integrator Frequency Locked Loop). The proposed technique is simulated using MATLAB/Simulink and conducted experimentally as well.

The increased demand for high power density converters resulted in increased EMI. This is addressed by considering all the converter parasitics along the noise propagation path. In this paper, the analytical approach for common mode (CM) noise analysis of dual active bridge (DAB) converter is presented. The dv/dt of CM voltage that excites the parasitic capacitances are the main source of CM noise. This CM noise is analysed by calculating the change in CM voltage from one state to another state for single phase shift technique (SPST) measured at LISN terminals. The CM noise for symmetrical and asymmetrical inductor and parasitic capacitors are also analysed using this approach. The analysis is thoroughly verified in LTspice with the parasitics measured from the hardware prototype.