This paper presents a dual-channel$\times 2$/$\times 3$broadband frequency multiplier based on a single core, capable of simultaneously realizing frequency doubling and tripling under single-band input. A modified Enz-Krummenacher-Vittoz (EKV) model combined with harmonic impedance analysis is employed to investigate both the concurrent generation of second and third harmonics and their mutual interaction. A multifunctional broadband output network is proposed to extract harmonics, provide impedance matching, and suppress unwanted frequency components. The frequency multiplier is implemented in 40 nm CMOS, occupying a core area of only 0.05 mm2. Measured results show a second harmonic output power of 2 dBm with a 3-dB bandwidth spanning 110–174 GHz, and a third harmonic output power of -3.8 dBm with a 3-dB bandwidth of 167–254 GHz, achieving a total bandwidth coverage exceeding 140 GHz. To the best of the authors’ knowledge, this work is the first non-injection-locked dual-channel frequency multiplier based on a single core in CMOS process. It also achieves the widest 3-dB bandwidth among CMOS or SiGe-based frequency doublers and triplers operating in the D-band and the 170–260GHz range.

This paper presents a compact gain-boosted up-conversion mixer integrated with input active balun in D-band. To simplify the driving stages of power amplifiers and enable large-scale integration in millimeter-wave systems, a proposed gain-boosted technique is introduced. This technique enhances the conversion gain of the mixer without increasing power consumption or footprint, achieved through the synergistic combination of negative resistance compensation (NRC) and current-reuse techniques. Furthermore, a wideband balance compensation technique is utilized at the local oscillator (LO) input, and an active balun is implemented at the intermediate frequency (IF) input, replacing the conventional large-area passive balun. These innovations lead to a more compact high-gain mixer design while achieving high-speed performance. For validation, the proposed up-conversion mixer is fabricated in a 40-nm CMOS. It boasts a total area of 0.15 mm2 ($0.033~\lambda ^{2}$), with a core area of 0.024 mm2 ($0.0052~\lambda ^{2}$). It achieves a measured conversion gain of 4.1 dB at 136 GHz. The measured saturation power is −5 dBm, with a data transmission rate of 42 Gbps, while consuming a power consumption of 10.8 mW only. To the best of our knowledge, this design achieves the highest conversion gain among D-band up-conversion mixers in CMOS technology and represents the smallest footprint among up-conversion mixers integrated with balun in D-band.

This manuscript introduces an integrated power amplifier (PA) meticulously designed for the D-band, addressing the interconnect challenges between power amplifiers and transmitting antennas operating in the millimeter-wave and terahertz frequency ranges. The proposed PA design is founded on a 2-way combined, low-loss balanced amplifier technology. The low-loss balanced amplifier technology utilizes a four-stage differential common-source amplifier unit, featuring the lossy over-neutralization technique as foundational building blocks. Simultaneously, the combining network integrates a quadrature coupler designed with a novel slow-wave coupled line. In contrast to conventional coupled line structures, the novel slow-wave coupled-line structure excels in low loss, high coupling coefficient, and the demand for high characteristic impedance while maintaining a high phase constant, contributing to a more compact form factor. Fabricated utilizing a 40-nm CMOS process, the amplifier showcases a total area of 0.34 mm2 ($0.074\lambda ^{2}$), with a core area of 0.11 mm2 ($0.024\lambda ^{2}$). At 130 GHz, it attains a peak gain of 23 dB, a saturated output power of 13.2 dBm. Moreover, the entire D-band exhibits outstanding matching characteristics. To the best of our knowledge, this is the first published CMOS balanced power amplifier designed in D-band.