Near-DRAM computing strategies advocate for providing computational capabilities close to where data is stored. Although this paradigm can effectively address the memory-to-processor communication bottleneck, it also presents new challenges: The strict resource constraints in the memory periphery demand careful tailoring of architectural elements. We herein propose a novel framework and methodology to explore compute-near-memory designs that interface to DRAM memory banks, demonstrating the area, energy, and performance tradeoffs subject to the architectural configuration. We exemplify this methodology by conducting two studies on compute-near-bank designs: 1) analyzing the interaction between control and data resources, and 2) exploring the integration of processing units with different DRAM standards. According to our study, the optimal size ratios between instruction and data capacity vary from$2\times $to$4\times $across benchmarks from representative application domains. The retrieved Pareto-optimal solutions from our framework improve state-of-the-art designs, e.g., achieving a 50% performance increase on matrix operations with 15% energy overhead relative to the FIMDRAM design. In addition, the exploration of DRAM shows the interplay between available internal bandwidth, performance, and area overhead. For example, a threefold increase in bandwidth rises performance by 47% across workloads at a 34% extra area cost.

1-diode 1-Voltage controlled magnetic anisotropy (1D-1VCMA) can be an option for Storage Class Memory (SCM) to bridge the latency gap between DRAM and flash memory. It has low sneak current, high non-linearity and low IR drop. This paper presents the Design Technology Co-optimization (DTCO) study of 1D-1VCMA stack to improve the performance and energy. Thanks to precessional switching of VCMA, the write operation is very fast, but the read determines overall latency as read before write is needed to ensure reliable write operations. The read performance of 1D-1VCMA is penalized due to high VCMA MTJ resistance, hence impacting the overall performance. To improve the read performance, this paper explores two solutions: 1) reducing the VCMA RA product, and 2) improving the read circuit. These solutions improve the read performance by 36% and 260%, respectively.

Main memory system design and corresponding technology requirements have become increasingly challenging for data-dominated high-performance applications. To address the leakage and scalability issues of the conventional DRAM-based memory, new memory technologies with ultra-low leakage and potential for high scalability have been explored extensively over the last decade. However, none of them are mature enough to serve as a drop-in replacement for DRAM. In this paper, we propose a hybrid main memory system solution for utilizing new memory technologies with specific features, based on the target application characteristics and system configurations. To this end, we examine two new memories, 1S-1VCMA and IGZO-based DRAM, along with conventional DRAM in the context of hybrid main memory solutions for high-capacity and low-power Pareto-optimizations, respectively. To better evaluate the power and performance, we consider the page-fault modeling in our evaluations. The results of the simulation show that different combinations of memory technologies in the hybrid memory system, different memory capacities, and different storage systems could provide a promising solution in the system regarding the characteristics of running applications and the requirements of the system.

One of the main issues in Solid State Drive (SSD)-based storage systems is endurance which is directly affected by the number of Program/Erase (P/E) cycles. The increment of P/E cycles increases the bit error rate threatening the reliability of SSDs. Erasure codes are used to leverage the reliability of storage systems but they also affect the number of P/E cycles based on their code pattern. A lower dependency between data and parities in the code pattern may lead to smaller number of P/E cycles providing better endurance. This paper introduces an Endurance Aware EVENODD (EA-EO), which minimizes the dependency between data and parities in the coding pattern. A simulation environment is used to compare the write-cycles of EA-EO with EVENODD in terms of different request size. The results show that the endurance improvement of EA-EO code could be as high as 44%. Furthermore, performance analysis of these codes in terms of parity construction and failure recovery shows that the number of XOR-operations is reduced in EA-EO compared to EVENODD.