This Innovative Practice Full Paper presents a multidisciplinary framework for using emerging computing systems in engineering education. The computing landscape is in the midst of significant changes. Hardware and software systems are becoming highly data intensive, specialized, parallel, and heterogeneous. With these developments, new applications across a wide range of disciplines are being enabled, from agriculture, mechanical and control systems, and many other physical sciences. For this reason, new approaches for teaching, via hands-on experiences, with these systems is needed. In this paper, we propose a novel framework that can be used to support learning objectives for these systems, at the intersection of multiple disciplines (e.g. computer science, data science, mechanical/aerospace/industrial/computer engineering). Specifically, we describe a flexible computing platform, that supports the exploration of custom hardware and software, interfaces, communications, and integrated system design. The RISC-V based system-on-chip architecture and supporting software and programming tools provide a unique opportunity for students to quickly learn advanced computing concepts critical to future computing systems. An implementation of the framework is described in the context of an important class of control applications, system identification and motion control. As these systems scale, analyzing non-linear system dynamics requires non-traditional approaches, e.g. using modern learning-based models and tools. The proposed approach allows for students to explore the impact of computing abstractions, data-intensive system design, and the potential for cross layer optimizations, while also learning key concepts related to parallel programming models and architectures. Based on this case study, we also provide an analysis and discussion of potential curricular activities that could leverage the framework. A key obstacle for such engineering education research, is the lack of familiarity that students in different disciplines have for the other fields of study, making a complete understanding of overall system design principles difficult. This paper presents a framework for multidisciplinary synergy that alleviates this problem and elevates computing systems to a potentially critical position in engineering education.

This research full paper explores the magnitude of added course fees and miscellaneous costs in an engineering program and how these fees impact lower socio-economic students. Previous work has examined the effects of added course fees and development boards on students from various socioeconomic backgrounds. While the study found that students of varying socioeconomic status did not agree that they felt "ostracized" as a result of added course expenses, the study did not examine whether students felt other, less severe feelings of exclusion or loss of identity in relation to engineering costs.This paper provides an in-depth exploration of the effects of added course expenses on students' sense of inclusion in Electrical and Computer Engineering Programs. Specific emphasis is placed on how student experience varies by socio-economic status, and the experience of low-socio-economic status is treated with particular interest. "Added course expenses" includes any development boards, parts, and personal computing resources (laptops) necessary for student success but not directly charged by the school for enrollment in a course.

This abstract is for a Full Paper in the category of Innovative Practice. In Electrical and Computer Engineering programs, we are increasingly seeing a digital divide between students who can study and work on assignments 24/7 from powerful laptops, and those students who are forced to rely on the college's fixed, limited access computer labs to succeed. This paper discusses a proposal to address this problem in a low-to-no cost way at California Polytechnic State University by issuing underprivileged students laptops that have been recently retired from faculty use. The paper looks at the cost implications (and opportunities) of performing a light refurbishment on old faculty units, and provides benchmarks of retired faculty machines against newer faculty laptops across a number of common Electrical Engineering computation tasks.

Continuous pursuit of higher performance and energy efficiency has led to heterogeneous SoC that contains multiple dedicated hardware accelerators. These accelerators exploit the inherent parallelism of tasks and are often tolerant to inaccuracies in their outputs, e.g. image and digital signal processing applications. At the same time, permanent faults are escalating due to process scaling and power restrictions, leading to erroneous outputs. To address this issue, in this paper, we propose a low-cost, universal fault-recovery/repair method that utilizes supervised machine learning techniques to ameliorate the effect of permanent fault(s) in hardware accelerators that can tolerate inexact outputs. The proposed compensation model does not require any information about the accelerator and is highly scalable with low area overhead. Experimental results show, the proposed method improves the accuracy by 50% and decreases the overall mean error rate by 90% with an area overhead of 5% compared to execution without fault compensation.

This Research Paper examines the question of whether fixed computer labs are still a necessary or important facet of the Electrical Engineering Laboratory Environment. Large academic computer labs stocked with high performance computing workstations have long been a major feature of Electrical and Computer Engineering programs. Historically they have been used throughout the curriculum for everything from running complex image processing algorithms in Matlab to simulating and synthesizing advanced digital designs with CAD tools like Vivado. As the cost of computation has declined, however, and as students increasingly bring their own high performance computing devices to the lab, it is no longer clear that workstation-based computer labs provide a significant benefit for student learning. This paper explores this topic by looking at student in-lab computer usage patterns and preferences for an introductory digital design course at California Polytechnic State University San Luis Obispo. Our research also quantifies the potential environmental savings institutions can achieve by moving away from workstation-based labs by comparing average energy usage from students using lab computers versus those using their own laptops.

This Research Work-In-Progress Paper explores potential causes of measured differences in mental health between students in a joint Computer Engineering Program and students in the two home departments (Electrical Engineering and Computer Science). California Polytechnic State University (Cal Poly) currently runs its Computer Engineering Program (CPE) as a joint offering of the Electrical Engineering (EE) and Computer Science and Software Engineering (CSSE) Departments. The curriculum for this program is made up of roughly 50% computer science courses and 50% electrical engineering courses. With the exception of a single senior level capstone course, all CPE courses are also available to (and in many cases required for) students from the two home departments. As a result of this blended curriculum, it has long been assumed that CPE students would have a similar experience and a similar level of mental wellness to their peers in EE and CSSE. A recent study conducted at Cal Poly, however, indicates that CPE students are substantially more likely to screen positive for risk of Serious Mental Illness (SMI) than their peers. This study uses qualitative interviews with CPE, EE, and CSSE students try to determine potential stressors unique to each program. This study also delves into the quantitative survey data to look for population specific trends that may be feeding into this result.

With the continuous sub-micron process scaling, reliability of integrated circuits has quickly become a first-order design concern. In modern computing systems, transient errors are increasingly likely to corrupt the computation by altering the control flow or sequencing of instructions, leading to catastrophic failures. Prior work on control flow checking provides good coverage but at a high cost. In this paper, by exploring regular control flow patterns found in most applications, we propose the optimization schemes for software signature control flow checking that could reduce the error detection overheads. Specifically, we leverage the fact that most applications have: (1) simple fan-in / fan-out control flow patterns, and (2) most of control flows can be predicted during the compilation stage through static branch prediction heuristics. By exploiting these opportunities, we propose two techniques to reduce the number of inserted codes at common paths and simplify control flow checking of irregular patterns with minimal overheads. Experimental results on a variety of applications demonstrate that our approaches could reduce checking overhead by almost 2.5x on average while leading to similar fault coverage compared to traditional control flow checking.

To handle the memory wall problem and satisfy the high processing speed of the multicore processors, there is significant demand for a large cache capacity in future. The 3D die-stacking DRAM cache with high density can be used as a large cache compared with conventional SRAM cache. However, energy becomes an inevitable challenge with the increasing size of DRAM cache. STT-RAM with near-zero leakage can be integrated with DRAM cache as a hybrid cache to reduce static energy, but the high write energy of STT-RAM brings another energy challenge. We observe that volatile STT-RAM can be utilized in the hybrid cache as a buffer to balance the high static energy of DRAM and the high dynamic energy of non-volatile STT-RAM.

Emerging die-stacked DRAM cache provides high bandwidth and low latency to break the memory wall. However, energy becomes a major challenge with the increasing size of die-stacked DRAM cache. It is observed that DRAM cache with longer bitlines consumes more energy due to larger capacitance. To reduce the high energy of long bitlines, we propose the TCache by partitioning every subarray of DRAM cache banks into three sublevels and schedule energy-efficient data movement among these levels based on reuse distance. We propose LevelMap and WayMap indicating in which sublevel and way that every data block of DRAM cache is located. Evaluations show these techniques can efficiently reduce energy consumption by 33.4% and improve performance by 10.6% on average.

With process scaling and the adoption of post-CMOS technologies, permanent faults are becoming a fundamental problem. Circuits containing defects are either discarded (reducing yield) or partially disabled (reducing performance). In this paper, we propose a general approach using supervised and discriminative learning techniques to compensate for the effect of permanent faults on a circuit's output. The insight for this approach is that many emerging systems and applications are able to tolerate some loss of quality in their computed results. Therefore, more scalable and lower overhead compensation techniques may be used to approximately correct for the effect of hardware faults on the circuit output. The proposed approach is shown to improve the output quality of complex accelerator and application-specific logic by 2-3 orders of magnitude while incurring

With process scaling and the adoption of post-cmos technologies, reliability and power are becoming a significant concern for future computing systems, especially highly parallel systems. Previous approaches have investigated augmenting applications with additional logic to detect and correct errors efficiently. In this research, we investigate the impact of different algorithmic designs on error resilience and propose an approach for algorithm selection for a class of equations, i.e. partial differential equations (PDEs), that are at the core of many scientific computing applications, which drive HPC systems. Many different schemes have been devised for the approximation of PDE systems, each with different accuracy, stability, and performance properties. In this research, there are two primary questions that we address: (1) Does numerical stability translate to error resilience? and (2) How do we design schemes to improve error resilience? If an algorithm's error resilience is correlated with its numerical stability properties, this may allow us to design more resilient applications by leveraging well established information on numerical stability. Even with a clear translation of numerical stability to error resilience properties, the question of designing these algorithms still remains however, due to the variety of implementations, schemes, and largely input specific nature of the design. In this research, we propose one approach for automated design using machine-learning. We observe that intelligent selection of the algorithm or a given problem, improves robustness by 20%-50%, on average, over the traditional selection of algorithms, without the addition of any other detection/correction logic.