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Charu Kalra

dblp:156/4677 · DBLP profile ↗
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6ranked-venue papers
1as first author
1since 2021 · last 2022
0009-0004-8952-7999ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 3Security and privacy · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 63% GPUs and heterogeneous computing · 37%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
soft errors
1.022022
Characterizing and Exploiting Soft Error Vulnerability Phase Behavior in GPU Applications · IEEE Trans. Dependable Secur. Comput. 2022
ArmorAll: Compiler-based Resilience Targeting GPU Applications · ACM Trans. Archit. Code Optim. 2020
GPUs and heterogeneous computing › GPU computing
GPU application reliability
0.612022
Characterizing and Exploiting Soft Error Vulnerability Phase Behavior in GPU Applications · IEEE Trans. Dependable Secur. Comput. 2022
Hardware reliability and fault tolerance › soft errors
transient fault propagation
0.612022
Characterizing and Exploiting Soft Error Vulnerability Phase Behavior in GPU Applications · IEEE Trans. Dependable Secur. Comput. 2022
GPUs and heterogeneous computing
GPU reliability
0.412020
ArmorAll: Compiler-based Resilience Targeting GPU Applications · ACM Trans. Archit. Code Optim. 2020
Hardware reliability and fault tolerance › soft errors
instruction duplication
0.412020
ArmorAll: Compiler-based Resilience Targeting GPU Applications · ACM Trans. Archit. Code Optim. 2020
GPUs and heterogeneous computing
GPU computing
0.212022
Characterizing and Exploiting Soft Error Vulnerability Phase Behavior in GPU Applications · IEEE Trans. Dependable Secur. Comput. 2022
Compilers and program optimization
compiler optimization
0.112020
ArmorAll: Compiler-based Resilience Targeting GPU Applications · ACM Trans. Archit. Code Optim. 2020

Methods — techniques the papers use, named apart from their topics

compiler-based instruction duplication · 0.9fault injection · 0.6
YearPublicationVenuePosition
2022 Characterizing and Exploiting Soft Error Vulnerability Phase Behavior in GPU Applications
abstract
System reliability has become a first-class design constraint. As the use of Graphics Processing Units (GPU) continues to increase in compute applications, including High Performance Computing (HPC) and safety-critical applications, so do the number of transient faults in GPUs. However, our understanding of the potential impact of transient fault propagation in GPU applications remains limited. This study shows that the resilience characteristics of GPU programs change significantly during program execution and these characteristics show repetitive, time-varying behavior. Interestingly, these repetitive, time-varying, resilience characteristics of GPU programs do not align or correlate well with the performance phases of GPU programs. Furthermore, this work discovers and validates that temporal changes in the vulnerability behavior during a kernel execution tends to coincide with changes in basic block execution paths. Finally, we demonstrate how these observations can be exploited to accelerate the fault injection campaigns for reliability assessment of GPU programs by an order of magnitude and open opportunities for designing other effective resilience mitigation strategies.
Fritz Previlon, Charu Kalra, Devesh Tiwari, David R. Kaeli
IEEE Trans. Dependable Secur. Comput.2
2020 ArmorAll: Compiler-based Resilience Targeting GPU Applications
abstract
The vulnerability of GPUs to soft errors has become a first-class design concern as they are increasingly being used in accuracy-sensitive and safety-critical domains. Existing solutions used to enhance the reliability of GPUs come with significant overhead in terms of area, power, and/or performance. In this article, we propose ArmorAll, a light-weight, adaptive, selective, and portable software solution to protect GPUs against soft errors. ArmorAll consists of a set of purely compiler-based redundancy schemes designed to optimize instruction duplication on GPUs, thereby enabling much more reliable execution. The choice of the scheme determines the subset of instructions that must be duplicated in an application, allowing adaptable fault coverage for different applications. ArmorAll can intelligently select a redundancy scheme that provides the best coverage to an application with an accuracy of 91.7%. The high coverage provided by ArmorAll comes at an average improvement of 64.5% in runtime when using the selected redundancy scheme as compared to the state-of-the-art.
Charu Kalra, Fritz Previlon, Norman Rubin, David R. Kaeli
ACM Trans. Archit. Code Optim.1
2019 PCFI: Program Counter Guided Fault Injection for Accelerating GPU Reliability Assessment
abstract
Reliability has become a first-class design objective for GPU devices due to increasing soft-error rate. To assess the reliability of GPU programs, researchers rely on software fault-injection methods. Unfortunately, software fault-injection process is prohibitively expensive, requiring multiple days to complete a statistically sound fault-injection campaign. Therefore, to address this challenge, this paper proposes a novel fault-injection method, PCFI, that reduces the number of fault injections by exploiting the predictability in fault-injection outcome based on the program counter of the soft-error affected instruction. Evaluation on a variety of GPU programs covering a wide range of application domains shows that PCFI reduces the time to complete fault-injection campaigns by 22% on average, without sacrificing accuracy.
Fritz Previlon, Charu Kalra, Devesh Tiwari, David R. Kaeli
DATE2
2018 Evaluating the impact of execution parameters on program vulnerability in GPU applications
abstract
While transient faults continue to be a major concern for the High Performance Computing (HPC) community, we still lack a clear understanding of how these faults propagate in applications. This paper addresses two particular aspects of the vulnerabilities of HPC applications as run on Graphics Processing Units (GPUs): their dependence on input data and on thread-block size. To characterize fault propagation as a function of input parameters, we leverage an ISA-level fault injection framework and carry out an extensive fault injection campaign to characterize the vulnerability of a suite of GPU applications. Our results show that the vulnerability of most of the programs studied are insensitive to changes in input values, except in less common cases when input values were highly biased, i.e., values that exhibit a special vulnerability behavior. For example, the multiplication property of any value with a zero value (zero times any number is equal to zero) makes it a biased input for multiplication operations. Our study also examines the effects of changing the GPU thread-block size and its impact on vulnerability. We found that, similar to performance, the vulnerability of an application can depend on the block size of the kernels in the application. In some applications, we found that the silent data corruption rate can vary by as much as 8% when changing the block size of a kernel.
Fritz Previlon, Charu Kalra, David R. Kaeli, Paolo Rech
DATE2
2015 NUPAR: A Benchmark Suite for Modern GPU Architectures
abstract
Heterogeneous systems consisting of multi-core CPUs, Graphics Processing Units (GPUs) and many-core accelerators have gained widespread use by application developers and data-center platform developers. Modern day heterogeneous systems have evolved to include advanced hardware and software features to support a spectrum of application patterns. Heterogeneous programming frameworks such as CUDA, OpenCL, and OpenACC have all introduced new interfaces to enable developers to utilize new features on these platforms. In emerging applications, performance optimization is not only limited to effectively exploiting data-level parallelism, but includes leveraging new degrees of concurrency and parallelism to accelerate the entire application.
Yash Ukidave, Fanny Nina Paravecino, Leiming Yu, Charu Kalra, Amir Momeni, Zhongliang Chen, Nick Materise, Brett Daley, Perhaad Mistry, David R. Kaeli
ICPE4
2014 Runtime Support for Adaptive Spatial Partitioning and Inter-Kernel Communication on GPUs
abstract
GPUs have gained tremendous popularity in a broad range of application domains. These applications possess varying grains of parallelism and place high demands on compute resources -- many times imposing real-time constraints, requiring flexible work schedules, and relying on concurrent execution of multiple kernels on the device. These requirements present a number of challenges when targeting current GPUs. To support this class of applications, and to take full advantage of the large number of compute cores present on the GPU, we need a new mechanism to support concurrent execution and provide flexible mapping of compute kernels to the GPU. In this paper, we describe a new scheduling mechanism for dynamic spatial partitioning of the GPU, which adapts to the current execution state of compute workloads on the device. To enable this functionality, we extend the OpenCL runtime environment to map multiple command queues to a single device, and effectively partitioning the device. The result is that kernels that can benefit from concurrent execution on a partitioned device can effectively utilize the full compute resources on the GPU. To accelerate next-generation workloads, we also support an inter-kernel communication mechanism that enables concurrent kernels to interact in a producer-consumer relationship. The proposed partitioning mechanism is evaluated using real world applications taken from signal and image processing, linear algebra, and data mining domains. For these performance-hungry applications we achieve a 3.1X performance speedup using a combination of the proposed scheduling scheme and inter-kernel communication, versus relying on the conventional GPU runtime.
Yash Ukidave, Charu Kalra, David R. Kaeli, Perhaad Mistry, Dana Schaa
SBAC-PAD2