A 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like gain calibrations is presented. The ADC includes an input buffer where its distortion is tackled by calibration. A low-cost auxiliary channel is introduced that serves as a reference for the calibration. It employs only a quarter of the input swing of the main channel, thus achieving adequate linearity. The auxiliary channel is further utilized for the gain calibration, where a split-ADC-like calibration is proposed to ease residue amplifier design constraint. The coefficients in the digital post-distortion filter are iterated through a multi-step multi-layer LMS algorithm, which converges faster and is more robust than its single-step counterpart. The buffered ADC works under a 1 V power supply thanks to the calibration, consuming 19.2 mW, where the input buffer contributes 18% of the total power. The calibration improves the SFDR by >14 dB within the 1st Nyquist zone, and >8dB up to 4th Nyquist input zone. The design achieves 59.3 dB SNDR and 67.1 dB SFDR at Nyquist input. The entire calibration converges within$1\times 10 ^{5}$iterations.

This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.