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Nesredin Mahmud

dblp:156/8053 · DBLP profile ↗
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7ranked-venue papers
4as first author
1since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 3 first-author · 1 since 2021Systems, architecture and hardware · 2 · 1 first-authorArtificial intelligence and machine learning · 1 · 1 first-authorTheory of computation · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Program verification · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program verification
model checking
0.212016
Simulink to UPPAAL Statistical Model Checker: Analyzing Automotive Industrial Systems · FM 2016
Program verification › model checking
statistical model checking
0.212016
Simulink to UPPAAL Statistical Model Checker: Analyzing Automotive Industrial Systems · FM 2016
Embedded and real-time systems
automotive systems
0.112016
Simulink to UPPAAL Statistical Model Checker: Analyzing Automotive Industrial Systems · FM 2016

Methods — techniques the papers use, named apart from their topics

simulink · 0.5UPPAAL · 0.5
YearPublicationVenuePosition
2024 SIMPPAAL: A Framework for Statistical Model Checking of Industrial Simulink Models
Predrag Filipovikj, Nesredin Mahmud, Cristina Cerschi Seceleanu, Guillermo Rodríguez-Navas, Oscar Ljungkrantz, Henrik Lönn
ISoLA (3)2
2018 Power-Aware Allocation of Fault-Tolerant Multirate AUTOSAR Applications
abstract
Software-to-hardware allocation plays an important role in the development of resource-constrained automotive embedded systems that are required to meet timing, reliability and power requirements. This paper proposes an Integer Linear Programming optimization approach for the allocation of fault-tolerant embedded software applications that are developed using the AUTOSAR standard. The allocation takes into account the timing and reliability requirements of the multirate software applications and the heterogeneity of their execution platforms. The optimization objective is to minimize the total power consumption of the applications that are distributed over multiple computing units. The proposed approach is evaluated using a range of different software applications from the automotive domain, which are generated using the real-world automotive benchmark. The evaluation results indicate that our proposed allocation approach is effective while meeting the timing, reliability, and power requirements of the considered automotive software applications.
Nesredin Mahmud, Guillermo Rodríguez-Navas, Hamid Faragardix, Saad Mubeen, Cristina Cerschi Seceleanu
APSEC1
2017 Specification and Semantic Analysis of Embedded Systems Requirements: From Description Logic to Temporal Logic
Nesredin Mahmud, Cristina Cerschi Seceleanu, Oscar Ljungkrantz
SEFM1
2016 ReSA Tool: Structured Requirements Specification and SAT-based Consistency-checking
abstract
Most industrial embedded systems requirements are specified in natural language, hence they can sometimes be ambiguous and error-prone.Moreover, employing an early-stage model-based incremental system development using multiple levels of abstraction, for instance via architectural languages such as EAST-ADL, calls for different granularity requirements specifications described with abstraction-specific concepts that reflect the respective abstraction level effectively.In this paper, we propose a toolchain for structured requirements specification in the ReSA language, which scales to multiple EAST-ADL levels of abstraction.Furthermore, we introduce a consistency function that is seamlessly integrated into the specification toolchain, for the automatic analysis of requirements logical consistency prior to their temporal logic formalization for full formal verification.The consistency check subsumes two parts: (i) transforming ReSA requirements specification into boolean expressions, and (ii) checking the consistency of the resulting boolean expressions by solving the satisfiability of their conjunction with the Z3 SMT solver.For validation, we apply the ReSA toolchain on an industrial vehicle speed control system, namely the Adjustable Speed Limiter.
Nesredin Mahmud, Cristina Cerschi Seceleanu, Oscar Ljungkrantz
FedCSIS1
2016 Simulink to UPPAAL Statistical Model Checker: Analyzing Automotive Industrial Systems
Predrag Filipovikj, Nesredin Mahmud, Raluca Marinescu, Cristina Cerschi Seceleanu, Oscar Ljungkrantz, Henrik Lönn
FM2
2014 Evaluating industrial applicability of virtualization on a distributed multicore platform
abstract
Adoption of virtualization technology has been limited in industrial automation due to unavailability of mature solutions, and strict timing requirements of control systems. However, current advancement in Virtual Monitoring Machine, multicore technology, virtualization extension and network virtualization has led to increased interest of virtualization in industrial automation. So far, many related research are focused on maximizing CPU and I/O utilization, and optimization applicable to soft realtime systems (i.e., outside industrial automation domain), e.g., multimedia applications. In this research, we make use of QoS for CPU, memory and network bandwidth in pursuit of high speed and predictability on a distributed multicore platform which is constructed entirely from open source products. We evaluate the platform for latency and jitter, network throughput and CPU computation load. Finally, we analyze the result for applicability in industrial control domain.
Nesredin Mahmud, Kristian Sandström, Aneta Vulgarakis Feljan
ETFA1
2014 The Multi-Resource Server for predictable execution on multi-core platforms
abstract
In this paper we present an implementation and demonstration of the Multi-Resource Server (MRS) which enables predictable execution of real-time applications on multi-core platforms. The MRS provides temporal isolation both between tasks running on the same core, as well as, between tasks running on different cores. The latter could, without MRS, interfere with each other due to contention on a shared memory bus. We demonstrate that MRS can be used to “encapsulate” legacy systems and to give them enough resources to fulfill their purpose. In our case study a legacy media-player is integrated with several resource-hungry tasks running at a different core. We show that without MRS the media-player starts to drop frames due to the interference from other tasks; while introduction of MRS alleviates this problem. Another part of our demonstration shows how traditional periodic real-time tasks can be kept schedulable even when tasks with high memory-demand are added to the system.
Rafia Inam, Nesredin Mahmud, Moris Behnam, Thomas Nolte, Mikael Sjödin
RTAS2