Logic locking is a well known Design-for-Security(DfS) technique for Intellectual Property (IP) protection of digital Integrated Circuits(IC). However, various attacks on logic locking can extract the secret obfuscation key successfully. Although Boolean Satisfiability (SAT) attacks can break most of the logic locked circuits, inability to deobfuscate sequential circuits is the main limitation of this type of attacks. Several existing defense strategies exploit this fact to thwart SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. In the absence of scan access, Model Checking based circuit unrolling attacks also suffer from scalability issues. In this paper, we propose a particle swarm optimization (PSO) guided attack framework, which is capable of finding an approximate key that produces correct output in most of the cases. Unlike the SAT attacks, the proposed attack framework can work even in the absence of scan access. Unlike Model Checking attacks, it does not suffer from scalability issues, thus can be applied on significantly large sequential circuits. Experimental results show that the derived key can produce correct outputs in more than 99% cases, for the majority of the benchmark circuits, while for the rest of the circuits, a minimal error is observed. The proposed attack framework enables partial activation of large sequential circuits in the absence of scan access, which is not feasible using the existing attack frameworks.

Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of several attacks, especially Boolean satisfiability attacks. This paper exploits SAT attack's inability of deobfuscating sequential circuits as a defense against it. We propose several strategies capable of preventing the SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. Unlike the existing SAT-resilient schemes, the proposed techniques do not suffer from poor output corruption for wrong keys. This paper also offers various probable solutions for inserting the key-gates into the circuit that ensures protection against numerous other attacks, which exploit weak key-gate locations. Along with several gate-level obfuscation strategies, this paper also presents a Cellular Automata (CA) guided FSM obfuscation strategy to offer protection at a higher abstraction level, that is, RTL-level. For all the proposed schemes, rigorous security analysis against various attacks evaluates their strengths and limitations. Testability analysis also ensures that none of the proposed techniques hamper the basic testing properties of the ICs. We also present a CA-based FSM watermarking strategy that helps to detect potential theft of the designer's IP by any adversary.

A popular countermeasure against IP piracy relies on obfuscating the Finite State Machine (FSM), which is assumed to be the heart of a digital system. In this paper, we propose to use a special class of non-group additive cellular automata (CA) called D1 * CA, and it's counterpart D1 * CAdual to obfuscate each state-transition of an FSM. The synthesized FSM exhibits correct state-transitions only for a correct key, which is a designer's secret. The proposed easily testable key-controlled FSM synthesis scheme can thwart reverse engineering attacks, thus offers IP protection.

Logic Encryption has emerged to be a promising solution to the ever-increasing problem of IP piracy and counterfeiting. The state-of-the-art logic encryption techniques fail to offer adequate protection to the designs, equipped with Design-for-Testability (DfT) infrastructure. In this paper, we propose a new logic encryption strategy which prevents scan-chain guided circuit partitioning attack by introducing circular dependency among all the keys irrespective of their locations. Leveraging the circular dependency, the proposed method can also thwart path sensitization, logic cone based, and SAT attacks without adopting any complex key-gate placement algorithms.

Logic encryption is a popular technique to safeguard an IC design from different security vulnerabilities. However, several recently proposed attacks exploit the weakness in key-gate placement schemes to extract the secret keys of an encrypted design. Security of a logic encryption strategy highly depends on the locations of the key-gates in a circuit. Most of the state-of-the-art logic encryption schemes suffer from the fact that the defence strategies against different attacks demand different locations for the placement of the key-gates. Therefore, it becomes incredibly challenging for a single solution to thwart all the state-of-the-art attacks. In this paper, we address this issue and propose a strategy which judiciously selects the locations of the key-gates to prevent different attacks and simultaneously satisfies another fundamental criterion of logic encryption, i.e., high output corruption for wrong keys.

A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance and may even create deadlocks, which can raise serious concerns in time critical systems. A security unit has been proposed to detect these attacks and mitigate the consequent loss by guiding the control units of the corresponding buffers to either isolate or mask the attacked buffers in runtime. Area and power overheads of the proposed secure router are found to be a maximum of 1.69% and 0.63% respectively when compared to a baseline router in a 16×16 Mesh network. The proposed secure router can also improve the normalized execution time as well as energy consumption of benchmark applications under considered IPRAs.

Logic encryption is a popular technique to safeguard an IC design from different security vulnerabilities. However, several recently proposed attacks can extract the secret keys of an encrypted design. In this paper, we propose a new logic encryption strategy, which integrates an additional key generation unit with the design. The key generation unit takes external keys and performs a permutation of the keys to generate a highly interdependent key-set, which are applied to the inputs of the keygates. Experimentation on IWLS'05 benchmarks shows that our proposed strategy can thwart most of the existing attacks, thus enhances the security of logic encryption at the cost of reasonable design overheads.

The IEEE 1687 Standard specifies an access network and a description language for embedded instruments. In this paper, we present an optimization technique to minimize the segment insertion bit (SIB) programming overhead for IEEE 1687-compliant access architectures. We first present an optimal solution based on dynamic programming for concurrent access schedules. This technique is then utilized to minimize the SIB programming overhead for more general hybrid access schedules. The proposed optimization technique is computationally efficient and it leads to significant reductions (as large as 97%) in the SIB programming overhead for hybrid access schedules.

This paper presents a test infrastructure development and test scheduling strategy for 3D-SICs under resource (test pins and TSVs) and power constraints. Depending upon the various scheduling restrictions, two test scheduling strategies have been proposed with an objective to minimize the overall test time (TT) of the stack. A step-by-step approach deals with the individual dies separately and develops power-restricted test schedules for each die and finally decides test concurrency between the dies satisfying the resources and power limits of the stack. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation and power distribution to individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of the SIC. Another integrated approach uses PSO to generate power-constrained test schedule of the entire SIC in a single optimization step. Integrated approach produces better results than the step-by-step approach because of its higher flexibility with lesser restrictions. User may select any of the scheduling strategies depending upon the scheduling criteria.

This paper presents a test architecture optimization and test scheduling strategy for TSV based 3D-Stacked ICs (SICs). A test scheduling heuristic, that can fit in both session-based and session-less test environments, has been used to select the test concurrency between the dies of the stack. The proposed method minimizes the overall test time of the stack, without violating the system level resource and TSV limits. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation of individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of SIC. Experimental results show that upto 51% reduction in test time can be achieved using our strategy, over the existing techniques.