In this brief, a high-speed [multiway parallel (MWP)] hardware-implemented deflate data compressor (DDC) is proposed for reducing the storage of solid-state drives (SSDs). To minimize the area of the DDC, registers instead of static random access memories (SRAMs) are utilized for building hash tables because multiway data within the DDC are able to access a register-based hash table simultaneously. To further reduce the area of the DDC, the output data of indefinite length are concatenated with a tree-type hardware architecture for reducing the overall concatenation complexity. Moreover, a solid mathematical foundation is established for optimizing the latency values of Lempel–Ziv (LZ)77 circuit, the Huffman encoding circuit, and the output data concatenation circuit within the MWP DDC. The results show that the proposed MWP DDC is capable of achieving a 12.1-Gb/s throughput and a 1.76 compression ratio (CR) with a 1.17-mm2area and 0.103-$\mu $s latency, under the synthesis of SMIC 55-nm process design kits (PDKs). Hence, the proposed DDC satisfies the SSD compression requirement for a universal serial bus (USB) 3.2 connector.

In this brief, a high-speed secret merchant-4 (SM4) cryptographic circuit with strong robustness against differential power analysis (DPA) attacks is proposed for securing the wireless networks for the first time. To achieve a high-throughput design for the SM4 algorithm, 32-stage pipelined encryption rounds and key expansion rounds are employed. Moreover, to resist DPA attacks, one pseudorandom number generator (PRNG) is embedded to randomly alter the SM4 circuit with a 32-stage or 34-stage pipeline, the other PRNG is utilized for realizing redundant operations to further break the correlation between the processed data and power dissipation of the SM4 circuit. When compared to a regular SM4 cryptographic circuit, the proposed SM4 architecture is capable of achieving a high throughput and satisfactory robustness against DPA attacks without compromising much power, area, and performance overhead. The result shows that the pipelined SM4 cryptographic circuit achieves a 128-Gbps throughput and 47 423-$\mu$m$^2$area with a high measurement-to-disclosure (MTD) value ($>$1 million) after synthesizing in the SMIC 14-nm process design kits (PDKs).