We present a solution for reducing the number of defective analog/RF integrated circuits (ICs) that escape detection during manufacturing testing. Also known as underkill, these ICs may fail when deployed in their target application and eventually become customer returns, casting doubt on the effectiveness of the employed test solution and affecting the bottom line. To ameliorate this problem, we introduce an adaptive outlier detection solution that identifies ICs which are suspect of becoming customer returns and proactively bins them as failing. The outlier detection boundary used by our method is dynamically computed based on the performance distribution of devices on each wafer and the underlying model is updated when new ICs are returned from customers and failure analysis confirms that they are indeed defective devices. The effectiveness of our method in reducing underkill while minimizing the incurred yield loss is evaluated using an industrial dataset from Texas Instruments.

Increasing use of contract manufacturing services presents security challenges within a multi-tenant environment. This statement applies to all compute resources in and around the test cell. In this paper, we demonstrate that zero trust principles can be applied to provide a secure edge computing appliance with a temporary store for sensitive data.

In recent years, optical inspection has been necessary to ensure quality across multiple manufacturing processes. An example of such a process is IC socket production, where the visual examination of each pin is essential to guarantee its regular operation. This paper presents improvements in the current state-of-the-art automated IC socket pin defect detection solution. Details of the proposed methodology are provided, targeting performance enhancement and complexity reduction. To evaluate the proposed approach, we present prediction results for a large number of pins on a complex socket product.

Post-fabrication performance calibration, a.k.a. trimming, is an essential part of analog/RF IC manufacturing and testing. Its objective is to counteract the impact of process variations by individually fine-tuning the performance parameters of every fabricated chip so that they meet the design specifications and, thereby, to ensure both high yield and high performance. The prevalent trimming process currently employed in industry involves a search algorithm which consists of repeated digital trim-code selection and measurement in order to optimize the trimmed performance. With hundreds of trims commonly performed on contemporary analog/RF chips, this process becomes overly expensive. In this work, we discuss a machine learning-based approach that ameliorates this problem by leveraging inter-trim correlation. Specifically, our method relies on effectively trained regression models which use the measurements obtained through an intelligently selected and conventionally performed subset of trims, in order to accurately predict the optimal trim codes for the omitted trims. Thereby, as corroborated using data from an actual analog/RF IC currently in production, trim time can be drastically reduced without significantly affecting the accuracy of the selected trim codes.

Design hotspots are layout patterns which may cause defects due to complex design and process interactions. Several machine learning and pattern matching-based methods have been proposed to identify and correct them early during design stages. However, almost all of them suffer from high false-alarm rates, mainly because they are oblivious to the root causes of hotspots. In this work, we seek to address this limitation by using a novel database enhancement approach through synthetic pattern generation based on a carefully crafted design of experiments. We evaluate the effectiveness of the proposed method using industry-standard tools and designs and demonstrate more than$3\times $reduction in classification error in comparison to the state-of-the-art.

The paper will demonstrate the application of Deep Learning (DL) for the detection of defective tester sockets. The proposed methodology relies on images like those used for manual or rule-based inspection, commonly collected using Automated Optical Inspection (AOI) equipment. This work represents a practical example of the use of Machine Learning for achieving improved inspection-quality outcomes at a lower cost. The experimental evaluation of the proposed methodology was performed on production set of collected socket images.

To combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vmin) of a given Integrated Circuit. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vmincalibration search, by identifying the optimal wafer-level search parameters. The effectiveness of the proposed methodology is demonstrated on an industrial dataset.

Ensuring high reliability in modern integrated circuits (ICs) requires the employment of several die screening methodologies. One such technique, commonly referred to as die inking, aims to discard devices that are likely to fail, based on their proximity to known failed devices on the wafer. Die inking is traditionally performed manually by visually inspecting each manufactured wafer and thus it is very time-consuming. Recently, machine learning has been used to automate and speed-up the inking process. In this work, we employ on-line machine learning to address the practicability limitations of the current state-of the-art automated inking approach. Effectiveness is demonstrated on an industrial dataset of manually inked wafers.

Automated defect inspection in manufacturing of microscopic probes is an important task and often requires machine learning driven solutions. A supervised only approach can be challenging, because production manufacturing process typically have few defects, thus large amounts of labeled training data are generally not available. In this work, we instead employed multiple models in a multi-step process to achieve the end goal of identifying defect and non-defect probe tips.

We propose a machine learning-based solution for noise classification and decomposition in RF transceivers. Wireless transmitters are affected by various noise sources, each of which has a distinct impact on the signal constellation points. The proposed approach takes advantage of the characteristic dispersion of points in the constellation by extracting key statistical and geometric features that are used to train a machine learning model. The trained model is, then, capable of identifying the noise source fingerprint, comprised by single or multiple noise sources, for each affected device. Effectiveness of the model has been verified using constellation measurements from a combined set of simulated and actual silicon devices.

Continuous technology scaling and the introduction of advanced technology nodes in Integrated Circuit (IC) fabrication is constantly exposing new manufacturability issues. Design hotspots are one of such problems, which are a result of complex design and process interactions. These hotspots are known to vary from design to design and foundries expect such hotspots to be predicted early and corrected in the design stage itself, as opposed to a process fix for every hotspot, which would be intractable. Various efforts have been made in the past to address this issue by using a known database of hotspots as a source of information. Most of those works use either Machine Learning (ML) or Pattern Matching (PM) techniques to identify and predict hotspots in new incoming designs. Almost all of those methods suffer from high false-alarm rates, mainly because (i) they are oblivious to the root causes of hotspots, and (ii) a large hotspot database to learn from is generally not available. In this work, we try to address these limitations by using novel hotspot Design of Experiments (DOEs) and synthetic pattern generation approaches. We analyze the effectiveness of the proposed method against the state-of-the-art on a 45nm process, using industry standard tools and designs.

Post silicon trimming is extensively used to counter the effects of manufacturing process variation on certain critical electrical parameters of an integrated circuit (IC). Usually, trimming is performed iteratively by adjusting the resistance value of a trim circuit to specific discrete values. Test programs represent those values by codes and apply common search algorithms in order to find a code which makes a device (optimally) compliant to its design specifications. Consequently, manufacturing yield is increased significantly, yet at the expense of added test time and complexity. In this work, we introduce a novel methodology wherein a trained multivariate model is used to predict, adaptively for each wafer, the optimal starting point of the algorithm that searches for the trim code. Thereby, we seek to minimize the number of code changes that the search algorithm has to perform and, by extension, the overall trim time. In order to provide this prediction prior to wafer sort, so that simplicity of test-floor logistics does not get compromised, the predictive model is built using electrical test (e-test) measurements, which are available before wafer sort, and is trained through measurements from a set of early wafers. Effectiveness of the proposed method in reducing trim time is demonstrated on 370 wafers of an high performance device manufactured by Texas Instruments.

Manual wafer-level die inking is a common procedure for excluding die locations that are likely to be defective. Although this is a more cost-effective process, as compared to the expensive burn-in tests, it remains a labor-intensive step during IC testing. For each manufactured wafer, test engineers have to visually inspect every failure map in order to identify any regions where additional die need to be marked and discarded. Towards reducing this cost, we introduce a novel pattern recognition methodology to learn and automatically generate the inking patterns from the failure maps, thus eliminating the need for human intervention. Effectiveness is demonstrated on an industrial set of manually inked wafers.

We propose a methodology for dynamically selecting an optimal probe-test flow which reduces test cost without jeopardizing test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, based on an e-test signature which reflects how process variations have affected this particular wafer. The proposed method offers flexibility by optimizing test flow per process signature and its implementation is simple and compatible with most commonly used Automatic Test Equipment. Furthermore, unlike static test elimination approaches, whose agility is limited by the relative importance of the permanently dropped tests, the proposed method is capable of exploring test cost reduction solutions which achieve very low test escape rates. Decisions are made by an intelligent system which maps every point in the e-test signature space to the most appropriate probe-test flow. Training of the system seeks to optimize the test flow of each process signature in order to maximize test cost reduction for a given target of test escapes, thereby enabling exploration of the trade-off between test cost reduction and test quality. The proposed method is demonstrated on an industrial dataset of a million devices from a 65nm Texas Instruments RF transceiver.

Laser trimming is used extensively to ensure accurate values of on-chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed-loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed-loop control and speeding up the process. Predictions are obtained from waferlevel spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of laser-trimmed ICs.