This work exploits Colored-Petri-Nets (CPN) for the early reliability estimation of hardware accelerators, significantly reducing the complexity during early design stages aimed at safety-critical systems. Our method builds high-level models of complex hardware accelerators to estimate reliability, integrating circuit characterization and fine-grain fault simulations on fundamental structures. We evaluate our methodology using six architecture variants of an on-chip hardware accelerator for deep learning (GPUs’ Tensor Cores). The results demonstrate that our approach reduces evaluation costs by 118x, achieving accuracy levels of up to 93.5% compared to exhaustive RT-level fault injection campaigns, while enhancing engineering productivity for early-stage designs.

One of the biggest concerns of Automotive System-on-Chip (SoC) design is the strict safety requirements for their hazardous operative scenarios. Commonly, designers employ Safety Mechanisms (SMs) to mitigate the fault effects and improve the SoC's safety levels. During the development phases, metrics, such as the Fault coverage (FC), are used to validate the effectiveness of the SMs. However, achieving such metrics, as defined by automotive standards, demands additional verification steps, resorting to extensive Fault Injection (FI) campaigns. These usually require mature design stages (e.g., RT-Gate level) involving significant simulation times and several iterations until obtaining the desired FC. Therefore, there is a high demand for new methodologies enabling FC estimation, supporting early-stage exploration, and avoiding expensive redesign phases. This work proposes a methodology exploiting Colored Generalized Stochastic Petri Nets (CGSPN) to model the SoC's architecture at a high level for FC estimation. The method optimizes and reduces the FI campaigns and is intended as a powerful tool supporting the development cycles of SMs, e.g., Software Test Libraries (STLs). Our experiments on an automotive test case indicate that STLs can be validated at a high level with minimal accuracy loss (1.1% on average) by optimizing the fault list in 28%. The results also showed a meaningful speedup of up to 160x in the development process of STLs.

Safety-critical systems can cause catastrophic effects when particular failures occur during their operation. These systems, used in diverse domains, including automotive SoCs, incorporate Safety Mechanisms (SMs) to enhance their safety performance and meet certification standards (e.g., ISO26262). A critical measure of safety performance is the Diagnostic Coverage (DC) of SMs, determined through extensive and expensive Gate-Level Fault Injection (FI) campaigns, as recommended by ISO26262. To address this challenge, designers need early DC estimation methods to efficiently develop more reliable SMs by reducing simulation times, redesign stages, and computational resources. Our previous work proposed an interactive simulation framework based on Colored Generalized Stochastic Petri Nets (CGSPN) for Fault Coverage (FC) estimation. This work incorporates the requirements of automotive safety standards to predict the efficiency of SMs. We propose a methodology for early-stage estimation of the DC, enabling efficient SM development and its Design Space Exploration (DSE), and the discovery of Failure Modes through CGSPN simulations. To the best of our knowledge, the proposed work is the first DC estimation approach based on high-level models such as CGSPN. The methodology was verified in an automotive SoC, showing an average estimation accuracy of 97.2% and a 175x speed-up for a Software Test Library (STL) compared to results obtained through an exhaustive RTL FI campaign.

Embedded systems’ hardware and software stacks are becoming more complex requiring more development time, time to market, and cost, which contributes to delayed delivery of these silicon devices. A virtual prototype (VP) provides an embedded systems architecture simulator for application development and testing purposes. In this paper, we developed and present the first virtual prototype of the Xtensa LX7 microprocessor that evaluates the performance of its emulated hardware performance counters (HPCs) with those collected from an actual Xtensa LX7 hardware. Seven machine learning models were developed and trained to find the relationships between the two different datasets for the sample application of classifiying return-oriented programming (ROP) attacks. Our experiments show that the obtained micro-architectural characteristics on the VP are on average about 70% similar and thus permit early simulation capabilities for developers and testers.

Several simulations have been performed in order to verify the system architecture behavior, showing that the dynamic reconfiguration time overhead is mainly due to the packet draining time. The synthesis results obtained a maximum frequency of 182.02MHz (Virtex 4) and 162.86MHz (Virtex 6) for both 5×5 and 8×8 meshes respectively. Table I shows the synthesis results for a 5-port 16-bit router and MRCS logic for a 5×5 mesh.