Drawing on neuroscience, we have developed a parallel, event-driven kernel for neurosynaptic computation, that is efficient with respect to computation, memory, and communication. Building on the previously demonstrated highly optimized software expression of the kernel, here, we demonstrate True North, a co-designed silicon expression of the kernel. True North achieves five orders of magnitude reduction in energy to-solution and two orders of magnitude speedup in time-to solution, when running computer vision applications and complex recurrent neural network simulations. Breaking path with the von Neumann architecture, True North is a 4,096 core, 1 million neuron, and 256 million synapse brain-inspired neurosynaptic processor, that consumes 65mW of power running at real-time and delivers performance of 46 Giga-Synaptic OPS/Watt. We demonstrate seamless tiling of True North chips into arrays, forming a foundation for cortex-like scalability. True North's unprecedented time-to-solution, energy-to-solution, size, scalability, and performance combined with the underlying flexibility of the kernel enable a broad range of cognitive applications.

The architectural and implementation issues of a prototype of a low-level image segmentation architecture (LISA) are described. LISA performs real-time gray-level image segmentation. A decision-theoretic pattern recognition approach divided into feature extraction and decision analysis parts is used. The feature extraction part is based on extracting local and global descriptions of the image pixels. In the decision analysis part, the pixels are classified into one of the user-selected classes based on the extracted features. One of the main properties of the approach is that the feature extraction and decision analysis are performed in real time. The status of the hardware and software development of the LISA prototype for a variety of industrial inspection applications is described. The LISA architecture is being implemented using state-of-the-art VLSI technology.>