For scalar maximum distance separable (MDS) codes, the conventional repair schemes that achieve the cut-set bound with equality for the single-node repair have been proven to require a super-exponential sub-packetization level.As is well known, such an extremely high level severely limits the practical deployment of MDS codes.To address this challenge, we introduce a partial-exclusion (PE) repair scheme for scalar linear codes.In the proposed PE repair framework, each node is associated with an exclusion set.The cardinality of the exclusion set is called the flexibility of the node.The maximum value of flexibility over all nodes defines the \textit{flexibility} of the PE repair scheme. Notably, the conventional repair scheme is the special case of PE repair scheme where the flexibility is 1. Under the PE repair framework, for any valid flexibility, we establish a lower bound on the sub-packetization level of MDS codes that meet the cut-set bound with equality for single-node repair. To realize MDS codes attaining the cut-set bound under the PE repair framework, we propose two generic constructions of Reed-Solomon (RS) codes. Moreover, we demonstrate that for a sufficiently large flexibility, the sub-packetization level of our constructions is strictly lower than the known lower bound established for the conventional repair schemes.This implies that, from the perspective of sub-packetization level, our constructions outperform all existing and potential constructions designed for conventional repair schemes. Finally, we implement the repair process for these codes as executable Magma programs, thereby exhibiting the practical efficiency of our constructions.

Byzantine Fault Tolerance (BFT) protocols enable reliable consensus in distributed systems, even with malicious nodes. Synchronous BFT protocols provide the strongest fault tolerance, ensuring security as long as more than half the nodes are honest, leveraging cryptographic signatures implemented via asymmetric algorithms. This paper studies the possibility of eliminating the reliance on cryptographic signatures and trusted third parties to distribute public and private keys for synchronous BFT. We formulated a synchronous BFT problem where each node has an unbounded computational power and can have a private observation of a random variable. The joint distribution of all the random variables is known to all nodes. We call this problem Information-Theoretic BFT (IT-BFT). To maintain liveness, we partition the nodes into two layers, with Layer 1 containing at most one malicious node. The performance of a secure IT-BFT protocol is quantified using the consensus rate defined as the entropy of the consensus information gained per consensus round, and the consensus capacity of an IT-BFT problem is the supermum of consensus rate of all secure IT-BFT protocols. For a system with$n$nodes and$f$malicious nodes, we show that the Gács-Körner (GK) common information of the Layer 1 nodes is a lower bound on the consensus capacity, which is tight for a family of secure IT-BFT protocols when$n=2 f+1$. When$n \geq 2 f+2$, a better lower bound on the consensus capacity is obtained, which can be strictly higher than the GK common information bound.

Shift-XOR codes employ shift and bitwise exclusiveor (XOR) operations and have been applied in distributed storage systems (DSS) to reduce the encoding/decoding computation cost. In this paper, we study shift-XOR Locally Repairable Codes (LRCs) to reduce the computation costs of encoding, decoding, and repairing. By extending an existing bound for LRCs, we obtain a bound on fault tolerance capability relating to the storage overhead due to shifting. We then provide an explicit construction of shift-XOR LRCs that achieves this bound asymptotically in some cases. The proposed construction has a storage overhead of$O\left(k(n-k)^{2}\right)$bits, which becomes negligible as sequence length increases. Furthermore, we develop an efficient code conversion framework in the merge regime by leveraging locality and shiftXOR operations. Our conversion method reduces access cost while maintaining low computational complexity.

This paper presents an analog-assisted hybrid low-dropout regulator (LDO) with a wide load current range and fast transient response. The proposed design is composed of digital and analog loops of which the transient response is dictated by the digital portion. A fast approximation algorithm leveraging charge distribution reduces settling time significantly compared to linear and SAR approaches. A wide load range droop detector further improves transient response with negligible power overhead. The analog assisted circuits continuously provide current in response to the load current change without disturbing the loop dynamic. Implemented in a TSMC 180-nm standard CMOS technology, the LDO supports a 430 mA maximum load and ensures loop stability without external capacitors. It achieves a 480 mV undershoot at 430 mA with 100 ns edge time,$49~\mu $A quiescent current, and settling times of 225 ns and 260 ns for undershoot and overshoot at$C_{L}=0$pF when a 10-MHz clock is used. Measurement shows that activating the droop detector reduces undershoot by 54%.

This paper presents Hamster, a novel synchronous Byzantine Fault Tolerant protocol that achieves high throughput and weaker dependency on synchrony. Specifically, Hamster is the first to introduce coding techniques into synchronous BFT, addressing the challenges posed by higher fault tolerance requirements and significantly reducing communication complexity. Consequently, Hamster achieves linear throughput gains as the number of nodes increases, surpassing Sync HotStuff. Additionally, with minor modifications, Hamster can operate effectively in mobile sluggish environments, further reducing its dependency on strict synchrony. We implement Hamster, and experimental results highlight its performance advantages. Specifically, Hamster achieves$2.5\times $the throughput of Sync HotStuff in a network of 9 nodes, with this gain growing to$10\times $as the network scales to 65 nodes. This increasing throughput advantage makes Hamster more applicable to large-scale distributed systems.

This brief presents an open-loop current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) intended for ultralow power direct digitizing micro-sensors readout applications. The proposed highly linearized pseudo-differential${G}_{M}$-stage mitigates the harmonic distortions induced by the tune circuit to the nonlinear transfer characteristic of the voltage-controlled oscillator (VCO), and it improves the total SNDR considerably. The ADC is implemented in 180-nm CMOS and achieves a peak SFDR of 81.48 dB, THD of −76.8 dB, and SNDR of 70.9 dB (equivalent to 11.48 ENOB) over a 3.6 kHz bandwidth with a 110 mVPP input differential sinewave. A chopper is used for the input transconductance stage to mitigate the input-referred noise and its impact on output phase noise. The ADC consumes$20.3 \mu {\text {W}}$from a 1-V supply.

This paper presents a high-speed low dropout (LDO) regulator with wide dynamic range. The use of piecewise speed enhancement technique dividing the loop dynamic into three phases in which the current regulation circuits (CRC), large-signal derivative path control circuits addressing the design challenge of slew rate limitation, and the hybrid passive-active frequency compensation (PAFC) for small signal settling time improvements are introduced lends the proposed LDO to providing constant output voltage under the condition of large load variations. The LDO is designed in TSMC 180-nm 1.8 V standard CMOS technology with 0.17 mm2 active area. The quiescent current is 380$\mu \mathrm{A}$at no load. With regulated 1.2 V output, the input voltage ranges from 1.3 V to 1.8 V. The measured overshoot and undershoot with load steps of 0 to 100 mA at 50 ns edge time are 135 mV and 105 mV, respectively. The settling time at 25 mA, 50 mA and 100 mA are 2.6$\mu \mathrm{s}, 4.5\mu \mathrm{s}$, and 9.8$\mu \mathrm{s}$, respectively. The LDO is competent in handling a wide range of output capacitance from 0 to 5 nF while the overshoot and undershoot exhibits small variation in the load step response.

Abstract At FSE 2008, Leurent introduced the preimage attack on MD4 by exploiting differential trails. In this paper, we apply the differential-aided preimage attack to Keccak with the message modification techniques. Instead of directly finding the preimage, we exploit differential characteristics to modify the messages, so that the differences of their hashing values and the changes of given target can be controlled. By adding some constraints, a trail can be used to change one bit at a time and reduce the time complexity by a factor of 2. When the number of rounds increases, we introduce two-stage modification techniques to satisfy part of constraints as well. In order to solve other constraints, we also combine the linear-structure technique and accordingly give a preimage attack on 5-round Keccak[$r=1440,c=160,l=80$].

Operational transconductance amplifiers (OTAs) are widely employed as active elements in filters, data converters, and buffer amplifiers. Inverter-based implementation of OTAs is an attractive approach for low voltage realization of analog subsystems. However, there are still fundamental challenges such as how to simultaneously achieve high DC gain, bandwidth, speed, and good noise performance based on existing inverter-based OTA architectures. In this paper, a new two stage OTA, hybrid with current reuse inverter OTA and Nauta transconductor is proposed to improving performance by taking advantages of their own merits. The introduced architecture is keeping the merits of Nauta transconductor such as high bandwidth, high speed and the superior input referred noise performance of the current reuse inverter-based OTA. Furthermore, in order to reduce the PVT variations, bulk tuning circuits based on "detecting-feedback" loop applied on CMFB and the output stage of Nauta transconductor is proposed to dynamically tune the output DC levels under PVT variations. The proposed new hybrid OTA is implemented in 180nm CMOS technology and achieves very competitive performance compares with all inverter based OTAs and the other state-of-the-art OTAs.

A type-II analog phase-locked loop without charge pump and analog loop filter is proposed in this paper. A novel discrete proportional-integral-derivative circuit (DPIDC) is proposed to implement phase error integration and frequency compensation with time-domain processing. A phase-to-voltage converter (PVC) with a sample-and-hold is used to convert the phase error processed by the DPIDC to a voltage that controls the voltage-controlled oscillator (VCO). Simulation results in 180nm CMOS technology show the proposed DPIDC and PVC circuits only consume 6.5-μW power at 0.6-V supply voltage. The proposed PLL settles down steadily and achieves a normalized reference-spur rejection better than -84.6dBc.

In order to reduce computational complexity in data encoding, one can use bitwise shifts and logical XOR operations instead of more costly calculations, and apply a fast decoding method called zigzag decoding. Existing works on zigzag decoding usually design special generator matrices that enable certain zigzag solving algorithms. In this paper, we study this class of fast decoding methods holistically. The shift operations are represented by a shift matrix, whose entries are integers or a special infinity symbol. A negative entry signifies that some symbols are truncated, and an infinity symbol means that the corresponding input sequence is not involved in the encoding process. Two notions of solvability, called successive solvability and zigzag solvability, are formulated. The former is employed in most of the existing works on zigzag decoding, and is a special case of the latter one. We prove in this paper that these two notions of solvability are equivalent when the shift matrix have no negative entries. An equivalent condition for a successively solvable shift-XOR system is derived in terms of a directed graph, when the shift matrix has only finite entries. This characterization reveals the structure and the interconnections between the problem instances.

Storage codes using shift and XOR operations have been studied to achieve lower encoding and decoding computation costs, compared with the codes using large finite field operations. In this paper, we introduce a new class of shift-XOR codes using two-tone generator matrices, which generalize the existing increasing-difference generator matrices. Compared with the latter, our codes only have 1/3 to 1/2 storage overhead for practical cases, and have a decoding algorithm that preserves the desired properties. For two-tone shift-XOR codes, the reflected Vandermonde matrices achieve the smallest storage overhead; and for increasing-difference shift-XOR codes, the Vandermonde matrices achieve the smallest storage overhead. To verify the practical performance, we implement two-tone shift-XOR storage codes using C++ and compare the encoding/decoding throughput with the state-of-the-art implementation of Reed-Solomon codes. For certain practical cases, our codes can achieve from 50% to 100% higher encoding/decoding throughput than that of Reed-Solomon codes.

A monoshift matrix is a matrix that has binary polynomials of degree at most 1 as entries, and a monoshift system is a system of linear equations over polynomials with a monoshift coefficient matrix. We propose an algorithm called augmented elimination to reduce a monoshift matrix to a form called augmented echelon form of degree at most 1. The monoshift system in augmented echelon form can be solved efficiently by successive cancellation. We further derive a recursive formula of the rank distribution of a uniformly random monoshift matrix. For a square uniformly random monoshift matrix, the deficient-rank probability decreases to 0 almost exponentially fast as the matrix size increases. This is quite different compared with the square random matrices over a fixed finite field, where the deficient-rank probability increases when the matrix size increases. Certain coding problems can benefit from this special property of monoshift systems, as demonstrated by the applications in distributed storage systems with decentralized encoding and in batched network coding.

Decoding and repair schemes are proposed for shift-exclusive-or (shift-XOR) product-matrix (PM) regenerating codes, which outperform the existing schemes in terms of both communication and computation costs. In particular, for the shift-XOR minimum bandwidth regenerating (MBR) codes, our decoding and repair schemes have the optimal transmission bandwidth and can be implemented in-place without extra storage space for intermediate XOR results. Technically, our schemes involve an in-place algorithm for solving a system of shift-XOR equations, called shift-XOR elimination, which does not have the bandwidth overhead generated by shift operations as in the previous zigzag algorithm and has lower computation complexities compared with the zigzag algorithm. The decoding and repair of shift-XOR MBR/MSR codes are decomposed into a sequence of systems of shift-XOR equations, and hence can be solved by a sequence of calls to the shift-XOR elimination. As the decompositions of the decoding and repair depend only on the PM construction, but not the specific shift and XOR operations, our decoding and repair schemes can be extended to other MBR/MSR codes using the PM construction. Due to its fundamental role, the shift-XOR elimination is of independent interest.

In this paper, refined recovery and repair schemes are proposed for a storage system using the XOR-based MBR regenerating storage code proposed by Hou et al. Our schemes have zero transmission overhead for both recovery and repair, i.e., the total number of transmitted bits for repair/recovery is exactly equal to the total number of bits repaired/recovered. Further, our schemes use mainly XOR operations and have lower complexity than that of the previous schemes. Moreover, our schemes require only a small amount of auxiliary space, which qualifies our schemes as in-place.

This paper proposes a novel recovery scheme for the XOR-based storage codes with the increasing-difference property. For a message of kL bits stored in n storage nodes, a data collector connects any k out of the n storage nodes to recover the message. In our scheme, the data collector acquires exactly L bits for each node, so that no transmission overhead exists. Furthermore, we propose an in-place decoding algorithm that acquires less auxiliary space than the existing decoding algorithm, and the decoding computational complexity of our decoding algorithm is the same as the existing decoding algorithm.