EDBT 2026 Demo / reviewers in the wild / expert
Yuanquan Shi
dblp:157/5018
· DBLP profile ↗
12ranked-venue papers
1as first author
12since 2021 · last 2026
0000-0003-1162-9675ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 7 since 2021Artificial intelligence and machine learning · 4 · 1 first-author · 4 since 2021Security and privacy · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Ensemble multi-stream threshold network for malware open-set recognition
Zhanyu Chi, Yuanquan Shi, Qingzhong Liu |
Appl. Intell. | 3 |
| 2026 | Unsupervised anomaly detection in industrial IoT: A one-class tensor-train machine with randomized mapping
Xiaowu Deng, Yuanquan Shi, Rongbo Lu, Dunhong Yao, Chunqiao Mi, Jianhua Xia |
Knowl. Based Syst. | 2 |
| 2026 | Prefetching Mapping Table Entries to Speed Up Address Translation in DRAM-Less SSDsabstractCertain NAND flash-based storage devices are not equipped with dynamic random access memory (DRAM) for holding the whole mapping table, due to the constraints of chip size and the cost, such as secure digital cards. Such DRAM-less flash memory can load only a subset of frequently accessed mapping table entries into a limited-capacity, on-board static random access memory (SRAM) cache, to expedite address translation. To improve the use efficiency of the SRAM cache, this article proposes to prefetch mapping table entries into the cache according to their locality . Then, it can minimize the number of translation page reads at the flash array caused by loading the required entries, thus improving I/O performance. Specifically, we use the indicator of runs test to reflect the locality of mapping table entries on the same translation page. When processing a missed mapping entry, it determines whether adjacent mapping entries accompanying the missed one should be loaded into the cache or not, on the basis of the runs of the target translation page. Consequently, subsequent requests requiring access to these mapping entries can be quickly responded to with the cached ones, instead of reading the target translation pages. In addition, we support cache management based on the runs test of the mapping entries to further improve the cache hit ratio. Experimental results show that our proposal can increase the hit ratio of mapping table entries by 39.4 % and reduce overall I/O latency by 23.4 % on average, in contrast to state-of-the-art schemes. Zhibing Sha, Jun Li 0062, Zhigang Cai, Yuanquan Shi, Jianwei Liao 0001 |
ACM Trans. Storage | 5 |
| 2026 | Cache Partition Management for Improving Fairness and I/O Responsiveness in NVMe SSDsabstractNVMe SSDs have become mainstream storage devices thanks to their compact size and ultra-low latency. It has been observed that the impact of interference among all concurrently running streams (i.e., I/O workloads) on their overall responsiveness differs significantly, thus leading to unfairness. The intensity and access locality of streams are the primary factors contributing to interference. A small-sized data cache is commonly equipped in the front-end of SSDs to improve I/O performance and extend the device's lifetime. The degree of parallelism at this level, however, is limited compared to that of the SSD back end, which consists of multiple channels, chips, and planes. Therefore, the impact of interference can be more significant at the data cache level. In this paper, we propose a cache division management scheme that not only contributes to fairness but also boosts I/O responsiveness across all workloads in NVMe SSDs. Specifically, our proposal supports long-term data cache partitioning and short-term cache adjustment with global sharing, ensuring better fairness and further enhancing cache utilization efficiency in multi-stream scenarios. Trace-driven simulation experiments show that our proposal improves fairness by an average of66.0% and reduces overall I/O response time by between3.8% and18.0%, compared to existing cache management schemes for NVMe SSDs. Fan Yang 0110, Zhibing Sha, Zhigang Cai, Balazs Gerofi, Yuanquan Shi, Jianwei Liao 0001 |
IEEE Trans. Parallel Distributed Syst. | 7 |
| 2025 | ConvNeXt_GHSA: Integrating hybrid gated attention for malware image classification
Junhai Li, Yuanquan Shi |
J. Inf. Secur. Appl. | 3 |
| 2024 | Fast Online Reconstruction for SSD-Based RAID-5 Storage SystemsabstractNAND based solid state drives (SSDs) are almost ubiquitously used in safety-critical systems, and recent advances have demonstrated RAID implementations that built on the top of SSDs can effectively enhance the data integrity and reliability. RAID can restore the lost data chunks in case of failures of RAID components (i.e., SSDs in the context), through a process of RAID reconstruction. Specially, online RAID reconstruction allows the RAID system to continue fulfilling user I/O requests during reconstruction. Servicing user I/O requests, however, significantly affects the performance of reconstruction due to contention for the shared SSD bandwidth. This paper proposes a fast online reconstruction method for SSD-based RAID systems, that preferably restores the lost chunks if the replaced SSD device is idle to reduce the reconstruction time, thus minimizing the probability of a second disk failure in the RAID system during reconstruction. Furthermore, it schedules the tasks of restoring data/parity chunks according to the their impacts on other working SSDs in the RAID system, for the purpose of reducing the overall I/O latency. Through a series of experiments based on the selected disk traces of real-world applications, we show that the proposed reconstruction scheme can reduce the reconstruction time by up to 45.6%, and meanwhile cut down the I/O latency by 9.8% on average compared to state-of-the-art methods. Haodong Lin, Junhao Luo, Jun Li 0062, Zhibing Sha, Zhigang Cai, Yuanquan Shi, Jianwei Liao 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 6 |
| 2023 | Theories, algorithms and applications in tensor learning
Xiaowu Deng, Yuanquan Shi, Dunhong Yao |
Appl. Intell. | 2 |
| 2023 | Adaptive Management With Request Granularity for DRAM Cache Inside nand-Based SSDsabstractMost flash-based solid-state drives (SSDs) adopt an onboard dynamic random access memory (DRAM) to buffer hot write data. Then, the write or overwrite operations can be absorbed by the DRAM cache, given that there is sufficient locality in the applications’ I/O access pattern, to consequently avoid flushing the write data onto underlying SSD cells. After analyzing typical real-world workloads over SSDs, we observed that the buffered data of small-size requests are more likely to be reaccessed than those of large write requests. To efficiently utilize the limited space of DRAM cache, this article proposes an adaptive request granularity-based cache management scheme for SSDs. First, we introduce a request block corresponding to a write request, as the cache management granularity, and propose a dynamic manner for classifying small and large request blocks. Next, we design three-level linked lists for supporting different routines of upgradation for small and large request blocks, once their data have been hit in the cache. Finally, we present a scheme of evicting the request blocks having the minimum cost in cache replacement, by taking both factors of access hotness and time discounting into account. Experimental results show that our proposal can yield improvements on cache hits and the overall I/O latency by21.8% and14.7% on average, compared to state-of-the-art cache management schemes inside SSDs. Haodong Lin, Jun Li 0062, Zhibing Sha, Zhigang Cai, Yuanquan Shi, Balazs Gerofi, Jianwei Liao 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |
| 2022 | DRAM Cache Management with Request Granularity for NAND-based SSDsabstractMost flash-based solid-state drives (SSDs) employ an on-board Dynamic Random Access Memory (DRAM) to cache hot data at the SSD page granularity. This can significantly reduce the number of flush operations to the underlying arrays of SSDs given that there is sufficient locality in the applications’ I/O access pattern. We observe, however, that in most I/O workloads over SSDs the buffered data of small sized requests are more likely to be re-accessed than those of larger requests, which also require more DRAM space for caching their data. Haodong Lin, Zhibing Sha, Jun Li 0062, Zhigang Cai, Balazs Gerofi, Yuanquan Shi, Jianwei Liao 0001 |
ICPP | 6 |
| 2022 | Unsupervised anomaly detection for network traffic using artificial immune network
Yuanquan Shi, Hong Shen 0001 |
Neural Comput. Appl. | 1 |
| 2021 | Block Attribute-aware Data Reallocation to Alleviate Read Disturb in SSDsabstractThis paper proposes a data reallocation method in RR processes, by taking account of block attributes including P/E cycles and read counts. Specifically, it can distribute the data in the RR block onto a number of available SSD blocks, to allow different blocks keeping their own near optimal (tolerable) read count. Then, it can reduce the number of read fresh operations and the number of raw bit errors. Through a series of simulation experiments based on several realistic disk traces, we demonstrate that the proposed method can decrease the read response time by between 15.11% and 24.96% and the raw bit error rate by 4.14% on average, in contrast to state-of-the-art approaches. Mingwang Zhao, Jun Li 0062, Zhigang Cai, Jianwei Liao 0001, Yuanquan Shi |
DATE | 5 |
| 2021 | A Novel CFLRU-Based Cache Management Approach for NAND-Based SSDs
Haodong Lin, Jun Li 0062, Zhibing Sha, Zhigang Cai, Jianwei Liao 0001, Yuanquan Shi |
NPC | 6 |