Mixed-cell-height VLSI circuits are widely used to meet various design requirements. Due to design for manufacturability (DFM) considerations such as layout-dependent effects (LDEs), drain-to-drain abutment (DDA), and pattern coloring for multiple patterning, different spacings between adjacent cells affect performance, modeled as discrete spacing costs. A state-of-the-art dynamic programming (DP) approach can address this problem but can only handle a few cell rows simultaneously due to its high complexity. In this article, we propose a novel DP algorithm that can solve the problem optimally and more efficiently. Additionally, several optimality-preserving reduction techniques are employed to derive full-chip optimal solutions for large-scale designs. Experimental results demonstrate that the proposed approach significantly outperforms existing methods in terms of total spacing cost and total displacement.

FinFlex standard cells have been proposed in sub-3 nm process nodes by TSMC to offer great design flexibility and a good trade-off between performance, power, and area efficiency. In the FinFlex technology, each cell type has a number of versions, varying in cell heights and threshold voltages, enabling flexible cell substitution for placement optimization. This paper presents the first work in the literature on standard cell legalization for the FinFlex technology, addressing cell version substitution, power efficiency, and minimum implant area (MIA) constraints. Our proposed algorithm comprises three stages: intra-row violationaware pre-processing considering timing and power levels, directed acyclic graph-based initial legalization with cell version substitution, and dynamic programming-based inter-row violation removal. Experimental results show the superior performance of our approach over a baseline using state-of-the-art techniques.

Dynamic programming (DP) plays a crucial role as the backbone of many core optimization algorithms across the physical design flow, including placement, clock tree synthesis, and routing. However, DP methods with quadratic or higher time complexities often face scalability challenges in large-scale designs. In this work, we propose a novel GPU-accelerated DP technique that can be broadly adaptable to various DP-based algorithms. As a case study, we present a GPU-accelerated detailed placement framework targeting mixed-cell-height designs, built upon an optimal DP formulation. By leveraging the massive parallelism of modern GPUs and incorporating advanced cost accumulation strategies, our approach consistently delivers optimal placement solutions while achieving an average runtime reduction of 96.6% and peak speedups exceeding 1600×. This work demonstrates the potential of GPU acceleration not only to overcome runtime bottlenecks but also to enhance design quality in advanced physical design tasks.

Mixed-cell-height VLSI circuits have been popularly adopted to meet different design requirements. Due to various design for manufacturability (DFM)-related considerations, such as layout dependent effects (LDEs), drain-to-drain abutment (DDA), and pattern coloring for multiple patterning, different spacings in terms of placement sites between each pair of adjacent cells may result in different performances, which are usually modeled as discrete spacing costs. To tackle such a discrete and spacing cost-aware detailed placement problem for mixed-cell-height designs, a state-of-the-art dynamic programming (DP)-based approach can only tackle few cell rows simultaneously due to its extremely high complexity. In this paper, we propose a novel DP algorithm that can optimally and much efficiently solve the problem. In addition, several optimality-preserving reduction techniques are also proposed to enable the possibility of full-chip optimal solution derivation for large-scale designs. Experiments considering two DFM considerations show that the proposed approach greatly outperforms existing studies in terms of the total spacing cost, the total displacement, and runtime.

MOTIVATION: PIWI-interacting RNAs (piRNAs) are a class of small non-coding RNAs that are highly abundant in the germline. One important role of piRNAs is to defend genome integrity by guiding PIWI proteins to silence transposable elements (TEs), which have a high potential to cause deleterious effects on their host. The mechanism of piRNA-mediated post-transcriptional silencing was also observed to affect mRNAs, suggesting that piRNAs might play a broad role in gene expression regulation. However, there has been no systematic report with regard to how many protein-coding genes might be targeted and regulated by piRNAs. RESULTS: We trained a support vector machine classifier based on a combination of Miwi CLIP-Seq-derived features and position-derived features to predict the potential targets of piRNAs on mRNAs in the mouse. Reanalysis of a published microarray dataset suggested that the expression level of the 2587 protein-coding genes predicted as piRNA targets showed significant upregulation as a whole after abolishing the slicer activity of Miwi, supporting the conclusion that they are subject to piRNA-mediated regulation. AVAILABILITY AND IMPLEMENTATION: A web version of the method called pirnaPre as well as our results for browse is available at http://www.regulatoryrna.org/software/piRNA/piRNA_target_mRNA/index.php CONTACT: [email protected] or [email protected] SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.