This paper presents a compact, high-accuracy and scalable on-chip temperature sensor (TS) optimized for low-power embedded applications, such as system-on-chip (SoC) and microprocessor thermal monitoring. The proposed TS employs a capacitive-biased-diode (CBD) structure enhanced by an adaptive discharging period (ADP) technique to achieve high sensitivity and linearity without additional backend calibration. The CBD sensor output is digitized by an oversampling (OS) successive approximation register (SAR) ADC with custom vertical metal-oxide-metal (VMOM) capacitors and a mismatch error shaping (MES) technique, providing high accuracy in a minimized chip area. Additionally, a discharging clock chopping (DCC) technique is proposed to effectively suppresses low-frequency noise with minimal switch noise, while clock boosters are implemented to decrease the ON-resistance of switches, reducing nonlinearity effects. Fabricated in a standard CMOS 180nm process, the sensor occupies only 0.0251 mm2and consumes$3.6~\mu $W. It achieves a one-point trimmed inaccuracy of ±0.25°C over a temperature range of −40°C to 125°C.

Wake-up receivers (WuRXs) help to cut down the average power consumed by the wireless devices in the Internet of things (IoT). Compared to the non-standard designs, the standard (e.g. BLE-compliant) WuRX chips can be integrated seamlessly into the widely-deployed infrastructures, while there are more design challenges since the BLE-compliant WuRX should be resilient to adjacent-channel interferes as well as realize a high sensitivity. In traditional BLE-compliant WuRXs, the interferes were suppressed by an FBAR filter or a low-noise local oscillator (LO) generator, with the penalty of sensitivity degradation or additional power consumption. The existing edge-combine LO generating method can cut down the power consumption, while the increased LO noise significantly degraded the signal-to-interference ratio (SIR) performance. In this work, we have demonstrated a BLE-compliant WuRX chip that improves both the SIR and sensitivity with low power dissipation. Instead of the conventional I/Q path with 90 degrees out of the phase, a pseudo-I/Q dual-downconversion structure is proposed to offer a WuRX driven by 120-degree-apart ultra-low-power LOs signals, which helps to improve the SIR performance due to the lower LO noise than the conventional edge-combine methods. In addition, a dummy down-converter based mismatch-cancellation technique is proposed to improve the image rejection ratio (IRR) and sensitivity. Fabricated by a 65nm CMOS process, the proposed BLE-compliant WuRX chip achieves -21dB SIR in the adjacent channel as well as -94dBm sensitivity at the cost of only$306\mu $W power.

Radio frequency (RF) power-harvesting technology is widely used by the temperature sensors inside high-voltage power-distribution cabinets, which avoids the safety risks caused by the use of batteries. Although the RF electromagnetic wave generated by high-voltage electric fields inside the cabinet can serve as the power supply, it suffers from unstable energy density. As a result, an external device is usually required to power up and read the temperature sensor, such as the near-field communication (NFC) reader of a smartphone. In this case, the RF harvester of the temperature sensor should be sensitive enough to enable a safe operating distance between the external reader and cabinet. Traditional methods combined an AC-DC rectifier and a DC-DC converter to provide a sufficient-high supply voltage for the sensing circuits, but the sensitivity was limited to −21dBm. In this work, an oscillator-enhanced energy-fusion power-harvesting technique is proposed to extend the power-transfer range of NFC. The harvester picks up the NFC energy to start up an oscillator, which enhances the power-harvesting sensitivity of other RF electromagnetic waves such as the 433MHz component in the cabinet. Then, the harvested DC voltage can be increased due to the power superposition of both the 13.56MHz and 433MHz tones. The proposed technique is implemented in a power-harvesting chipset fabricated in 55nm CMOS and 65nm CMOS processes. Measurement results show that the sensitivity of 433MHz power harvester is improved by 4.1dB due to the enhancement of the NFC excited oscillator, which also extends the NFC power-transfer range to 9cm.

Battery-free tags offer a power-efficient solution for the wireless connection in Internet of Things (IoT), where the backscatter communication that is compatible with widely-deployed protocols such as Bluetooth Low Energy (BLE) significantly reduces the hardware cost thanks to the seamless integration into the existing infrastructure. However, there are three main shortcomings in the existing battery-free BLE tags: 1)The tag-to-access point (AP, uplink) communication ranges are limited to 97 meters at -10dBm incident power, which are not long enough for some outdoor scenes. 2) The AP-to-tag (downlink) communication in the state of the arts has not exceeded a 1Mbps data rate and a 4m range, disabling remote tag configuration. 3)The tag-to-tag communication has not been realized in a battery-free way, which cannot construct a passive IoT network. In this work, we demonstrate an integrated bidirectional passive BLE chip that conducts battery-free BLE communication in tag-to-tablet/smartphone, tablet/smartphone-to-tag, and tag-to-tag modes. The chip is implemented in a 65nm CMOS process. An all-digital intermediate frequency (IF) shaping technique is proposed to extend the tag-to-tablet/smartphone (uplink) communication range to 160m at$7.16\mu $W power consumption and a -10dBm incident tone. In addition, a$2^{nd}$-order intermodulation (IM2) based charge-domain GFSK demodulation technique is proposed to enable 1Mbps 12m downlink communication at$6.8\mu $W power consumption, which realizes both tablet/smartphone-to-tag and tag-to-tag communication in a fully battery-free way. As a result, the bidirectional passive BLE chip offers a potential solution for future battery-free IoT mesh network.

On-chip oscillators are suitable for low-cost and compact IoT applications, but their temperature stability is relatively poor. This paper presents a temperature compensation technique to improve the stability of an on-chip digitally-controlled oscillator (DCO). The oscillation period of the DCO and the local temperature are simultaneously extracted by a capacitively-biased-diode sensor operating in a code-division-modulation manner. As the period and local temperature readouts are correlated, the proposed technique can achieve accurate temperature compensation despite of voltage variations. With a single-point trim, the proposed oscillator achieves a temperature stability of 18.4 ppm/°C and a voltage stability of 0.24%/V. It consumes a power consumption of 231 μW at an oscillation frequency of 20 MHz.

Content addressable memories (CAMs) are a promising category of computing-in-memory (CiM) elements that can perform highly parallel and efficient search operations for routers, pattern matching, and other data-intensive applications. Various magnetic tunnel junction (MTJ)-based CAM designs have been proposed to realize zero standby power and high-performance search. However, due to the relatively small tunnel magneto-resistance (TMR) ratio, MTJ-based CAMs require extra transistors and differential MTJ branches to distinguish between the parallel and anti-parallel resistance states, resulting in significant area and energy overhead. In this article, we propose a device-circuit co-design approach for an ultracompact CAM design by only exploiting a 1T-1MTJ structure in each cell. We propose a 2-step search scheme to enable the parallel in-memory search operation across the proposed CAM array and demonstrate the sufficient sensing margin of the array in a successful search operation. Evaluation results suggest that our proposed 1T-1MTJ-based CAM design improves$179\times /301\times $area efficiency compared with the state-of-the-art 15T-4MTJ/20T-6MTJ CAM design. Application benchmarking on hyperdimensional computing (HDC) inference shows a$54.6\times /12.8\times $speedup compared with GPU/20T-6MTJ CAM-based approaches.

The peripheral oxygen saturation (SpO2) reflects the metabolic capacity of the human body, which can be used in assessing or screening symptoms such as pulmonary embolism. Photoplethysmography (PPG) is a common method for SpO2 monitoring, while it suffers from interferences such as ambient light scattering, reflections, and motion artifacts. These interferences significantly degrade the accuracy of SpO2 monitoring. Filtering techniques are widely used to suppress the interferences in PPG signals. However, conventional PPG filtering techniques use a fixed window, which is not able to handle interferences at different frequencies. In this paper, we propose a flexible-window filtering technique to suppress the interferences in SpO2 monitoring. To validate the proposed technique, we built a prototype to monitor the in-vivo SpO2 of the human body. Measurement results show that the proposed technique reduces the mean absolute percentage error (MAPE) of SpO2 by 46% compared to the conventional methods.

The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the$2^{\mathrm{nd}}$-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show −92 dBc/Hz@10 kHz phase noise and 6.8$\mu \text{W}$power.

A mixed-signal adaptive filter is proposed which can work with level-crossing ADC to maintain its energy efficiency and signal quality even under powerline interference. The adaptive filter adopts a novel phase and amplitude tracking method which does not require multibit multiplication as the conventional least mean square (LMS) adaptive filter does. It tracks the 60 Hz interference and generate an analog compensation signal to cancel it. This technique improves the powerline interference rejection at 60Hz by 28dB. From MATLAB simulation, it effectively reduces the unnecessary sampling caused by powerline interference of the LC-ADC by 94.4%.