Demo Data from EDBT 2026 / reviewers in the wild / expert
Yuan Xie 0008
dblp:157/8128-8
· DBLP profile ↗
7ranked-venue papers
3as first author
7since 2021 · last 2026
0000-0002-0771-4992ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 1 first-author · 2 since 2021Databases, data management, data science and information retrieval · 2 · 1 first-author · 2 since 2021Systems, architecture and hardware · 1 · 1 since 2021Computer networks · 1 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 70% GPUs and heterogeneous computing · 23% Processor architecture and microarchitecture · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › in-memory computing
near-bank computing |
0.7 | 1 | 2023 | MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing · ACM Trans. Archit. Code Optim. 2023 |
Memory systems
processing-in-memory |
0.7 | 1 | 2023 | MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing · ACM Trans. Archit. Code Optim. 2023 |
Memory systems › processing-in-memory
processing-using-DRAM |
0.7 | 1 | 2023 | MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing · ACM Trans. Archit. Code Optim. 2023 |
GPUs and heterogeneous computing › GPU architecture
SIMT processor |
0.7 | 1 | 2023 | MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing · ACM Trans. Archit. Code Optim. 2023 |
Processor architecture and microarchitecture › multi-chip architecture
3d stacking |
0.2 | 1 | 2023 | MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing · ACM Trans. Archit. Code Optim. 2023 |
Methods — techniques the papers use, named apart from their topics
instruction offloading · 0.7hybrid pipeline · 0.7CUDA compilation · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | MPFN: A multi-perspective fusion network for multivariate time series analysis
Yuan Xie 0008, Baohua Qiang, Xianyi Yang, Rui-dong Chen |
Neurocomputing | 1 |
| 2026 | STEN: A spatio-temporal enhancement network for anomaly detection in industrial multivariate time series
Yuan Xie 0008, Baohua Qiang, Rui-dong Chen, Lirui Chen |
Inf. Sci. | 1 |
| 2026 | Cross-modal quaternion relation mining and gap bridging for image-text retrieval
Rui-dong Chen, Baohua Qiang, Xianyi Yang, Yuan Xie 0008, Lirui Chen |
J. Intell. Inf. Syst. | 5 |
| 2025 | Linear self-attention with multi-relational graph for knowledge graph completion
Weida Liu, Baohua Qiang, Rui-dong Chen, Yuan Xie 0008, Lirui Chen |
Appl. Intell. | 4 |
| 2025 | CLIP-based semantic refinement method for image-text retrievalabstractAbstract Although existing image-text retrieval methods show strong retrieval performance, they generally fail to explicitly model the subtle semantic difference within categories. To address this problem, we propose a new image-text retrieval method, called CLIP-based Semantic Refinement Method For Image-Text Retrieval (CLIP2SRITR). The proposed method consists of a modal alignment part and a semantic matching part, where the former is to learn better alignment between two modalities and the latter is to enhance the aggregation of image-text features intra-class. The pipeline helps model the distinction between image-text pairs with semantic information differences. In addition, CLIP2SRITR leverages additive angular margin for image-text retrieval loss function to maximize classification boundaries, achieving the goal of increasing intra-class similarity and inter-class variability. Through extensive experiments on three image-text benchmarks, e.g. Wikipedia, Pascal-Sentence, and NUS-WIDE, we show that CLIP2SRITR outperforms state-of-the-art methods, verifying the effectiveness of our method. Rui-dong Chen, Shuiping Guo, Baohua Qiang, Xianyi Yang, Yuan Xie 0008 |
Comput. J. | 7 |
| 2023 | MPU: Memory-centric SIMT Processor via In-DRAM Near-bank ComputingabstractWith the growing number of data-intensive workloads, GPU, which is the state-of-the-art single-instruction-multiple-thread (SIMT) processor, is hindered by the memory bandwidth wall. To alleviate this bottleneck, previously proposed 3D-stacking near-bank computing accelerators benefit from abundant bank-internal bandwidth by bringing computations closer to the DRAM banks. However, these accelerators are specialized for certain application domains with simple architecture data paths and customized software mapping schemes. For general-purpose scenarios, lightweight hardware designs for diverse data paths, architectural supports for the SIMT programming model, and end-to-end software optimizations remain challenging. To address these issues, we propose Memory-centric Processing Unit (MPU), the first SIMT processor based on 3D-stacking near-bank computing architecture. First, to realize diverse data paths with small overheads, MPU adopts a hybrid pipeline with the capability of offloading instructions to near-bank compute-logic. Second, we explore two architectural supports for the SIMT programming model, including a near-bank shared memory design and a multiple activated row-buffers enhancement. Third, we present an end-to-end compilation flow for MPU to support CUDA programs. To fully utilize MPU’s hybrid pipeline, we develop a backend optimization for the instruction offloading decision. The evaluation results of MPU demonstrate 3.46× speedup and 2.57× energy reduction compared with an NVIDIA Tesla V100 GPU on a set of representative data-intensive workloads. Xinfeng Xie, Peng Gu 0007, Yufei Ding 0001, Dimin Niu, Hongzhong Zheng, Yuan Xie 0008 |
ACM Trans. Archit. Code Optim. | 6 |
| 2021 | Attention Mechanism-Based CNN-LSTM Model for Wind Turbine Fault Prediction Using SSN Ontology AnnotationabstractThe traditional model for wind turbine fault prediction is not sensitive to the time sequence data and cannot mine the deep connection between the time series data, resulting in poor generalization ability of the model. To solve this problem, this paper proposes an attention mechanism‐based CNN‐LSTM model. The semantic sensor data annotated by SSN ontology is used as input data. Firstly, CNN extracts features to get high‐level feature representation from input data. Then, the latent time sequence connection of features in different time periods is learned by LSTM. Finally, the output of LSTM is input into the attention mechanism module to obtain more fault‐related target information, which improves the efficiency, accuracy, and generalization ability of the model. In addition, in the data preprocessing stage, the random forest algorithm analyzes the feature correlation degree of the data to get the features of high correlation degree with the wind turbine fault, which further improves the efficiency, accuracy, and generalization ability of the model. The model is validated on the icing fault dataset of No. 21 wind turbine and the yaw dataset of No. 4 wind turbine. The experimental results show that the proposed model has better efficiency, accuracy, and generalization ability than RNN, LSTM, and XGBoost. Yuan Xie 0008, Jisheng Zhao, Baohua Qiang, Luzhong Mi, Chenghua Tang, Longge Li |
Wirel. Commun. Mob. Comput. | 1 |