The rapid adoption of the open and extensible RISC-V instruction set architecture across diverse computing domains requires a thorough understanding of its security posture, particularly against hardware threats. While performance optimizations like speculative and out-of-order execution enhance throughput, they concurrently introduce vulnerabilities to Transient Execution Attacks (TEAs), which can bypass traditional security mechanisms. The inherent flexibility of RISC-V leads to significant microarchitectural variation among implementations, suggesting that susceptibility to TEAs is not uniform. However, systematic comparative assessments across prominent processors are still lacking. This paper addresses this gap by presenting a comparative vulnerability analysis of three widely used open-source RISC-V cores: the high performance BOOM, the reliability-oriented NOEL-V, and CVA6. We ported and evaluated a set of TEAs, including variants of Spectre and Meltdown and the most recent attacks, such as Speculative Code Store Bypass (SCSB) and Indirector. Our experiments demonstrate the successful execution of different attack subsets on each processor, revealing distinct vulnerability profiles tied to their underlying microarchitectures, offering valuable vulnerability data and practical insights that may be crucial for guiding the design of more secure processors. One of the key insights of our analysis is that, contrary to the popular belief, in-order processors are vulnerable against TEAs.

RISC-V is increasingly considered a strategic architecture for technological sovereignty and long-term platform independence, yet its practical maturity across software, performance and security is still debated. This paper presents an integrated, hardware-grounded assessment of the current RISC-V ecosystem. We first analyze software readiness by examining toolchain fragmentation, operating-system integration, and deployment effort across commercial ASIC boards and configurable FPGA soft-cores. We then benchmark representative processors using CoreMark, Geekbench 6, and SPEC2017, and contextualize the achieved results through direct comparison with contemporary ARM and x86 systems. Finally, we evaluate susceptibility to Transient Execution Attacks on three prominent open-source cores (BOOM, NOEL-V, and CVA6). The results show a clear three-way trade-off. Software support remains heterogeneous: ASIC platforms provide faster bring-up, whereas soft-core deployments require substantial hardware-software codesign effort. From a performance perspective, the best evaluated RISC-V ASIC demonstrates competitive per-cycle efficiency for embedded-class workloads, but a significant gap persists versus high-end proprietary processors; on FPGA soft-cores, low frequency and memory-system constraints often prevent completion of demanding benchmark suites. From a security perspective, all evaluated open-source cores are vulnerable to a subset of transient-execution attacks, with broader attack surfaces associated with more aggressive speculative microarchitectures. Overall, RISC-V is already a deployable opportunity for customizable embedded domains. For high-performance, general-purpose use, closing the gap requires coordinated ecosystem consolidation and rigorous security-by-design co-validation across hardware and software layers.

The open and modular nature of the RISC-V Instruction Set Architecture (ISA) has produced a fragmented landscape of hardware implementations and software environments, with direct consequences on portability, performance, and resilience to hardware attacks. The practical maturity of its most prominent cores, however, is rarely assessed in a unified manner and on real hardware rather than in simulation. This paper presents such an evaluation for six representative cores: three commercial ASICs (SiFive P550, Orange Pi RV2, Microchip PIC64GX) and three configurable FPGA-based soft-cores (BOOM, NOEL-V, CVA6). We study them along three complementary axes, namely the maturity of their software environments, distilled from hands-on deployment; their computational performance, measured with CoreMark, Geekbench 6, and SPEC2017 and contextualised against ARM and x86 cores; and the susceptibility of the open-source soft-cores to a comprehensive set of Transient Execution Attacks (TEAs). Our results identify the SiFive P550 as the strongest performer, comparable with mid-range embedded ARM cores but well behind high-end ARM and x86 designs; they show that the tested soft-core deployments are not yet ready for complex general-purpose workloads; and they reveal that even in-order cores are vulnerable to TEAs, with distinct profiles tied to their microarchitectures.

Transient Execution Attacks (TEAs) exploit architectural optimizations in modern processors, such as out-of-order and speculative execution, to illicitly access sensitive data belonging to other processes or the operating system. While the RISC-V ISA has gained significant traction, its susceptibility to TEAs remains relatively unexplored. A major obstacle to in-depth security evaluation of RISC-V processors is the lack of readily accessible and comprehensive TEA implementations for these architectures. This paper introduces Security for RISC-V (S4V), a security benchmark suite comprising implementations of several recent TEAs specifically tailored for RISC-V processors. Beyond providing a template for each TEA implementation, we developed an instance of S4V for the Berkeley Out-of-Order Machine (BOOM) processor to demonstrate the feasibility of executing these attacks on a widely adopted and renowned RISCV core. S4V aims to facilitate security research in evaluating countermeasures and enabling a more thorough understanding of TEA vulnerabilities within the RISC-V ecosystem.

Solar Active Regions are characterised by their intense magnetic activity, which often leads to solar phenomena such as solar flares, and coronal mass ejections (CMEs). With the recent advancement of computing technologies and the huge integration of Artificial Intelligence (AI), many approaches have been proposed for forecasting solar eruptions using machine learning. In this study, we propose the use of a Temporal Convolutional Network (TCN) for predicting whether an active region will be flaring in a specific window of time and defining the flare class. The dataset is categorised into three different subsets based on the flare class and trained separately with the same TCN architecture to apply late fusion. The proposed solar flare prediction ensemble (EoFNets) is based on both the physical characteristics of the active region (EoFPhyNet) and geometric features (EoFGeoNet). Experimental results show that TCN outperforms long short-term memory (LSTM) in three cases. Our main aim is to deploy deep-learning-based approaches onboard for faster and more accurate real-time monitoring as well as leveraging the higher sampling rates for improved time-series predictions. Many major benefits can be realised if the deep learning models can be implemented onboard, including a sizeable reduction in the volume of downlinked data, and improved system latency. However, implementing deep learning models in space can be a critical task, as most approaches require high computational and memory resources, both of which are limited in typical spacecraft onboard data handling systems. Nevertheless, the EoFNets network outlined in this paper has been optimised to fit the resource constraints of a space platform deployed at the extreme edge far from Earth. Two low-power hardware targets are considered, namely the IntelMovidius MyriadX and Rockchip RK3588S. To the best of our knowledge, this is the first time that such a TCN network has been proposed for solar flare forecasting.

High-criticality applications are vulnerable to Single Event Effects (SEEs) and require highly reliable and customizable microprocessors. Online checkers have been used to detect security and reliability issues in such systems. Popular hardware redundancy techniques such as Triple Modular Redundancy (TMR) and Dual Modular Redundancy (DMR) provide a high error coverage at the cost of substantial redundancy; therefore, there is an interest in introducing lightweight checkers that could offer the same detection ability as DMR with a much lower overhead. A possible implementation of these online checkers can be based on Probabilistic Data Structure (PDS) such as the Bloom Filter (BF). They are a form of information redundancy and an excellent complement to Single Error Correction Double Error Detection (SECDED) codes because they allow for detecting higher-order upsets. In this work, we integrate an online checker into the open-source RISC-V core NEORV32 and deploy it on a flash-based FPGA. This paper presents the evaluation of the online checker’s performance conducted under a neutron beam. The neutron beam experiments demonstrate that the real-life error rates of such structures are comparably worse than the initial simulation would indicate and that other factors can impact their performance.

This paper presents the MLAB project, a research and development activity funded by ESA General Support Technology Programme under the lead of Airbus Defence and Space GmbH, with the goal of developing a machine learning application benchmark for space applications. First, the need for a benchmark dedicated to machine learning applications in spacecraft is explained, and examples of applications are described including their design challenges. Then the benchmark design is presented, including the rules of the metrics, guidelines and scenarios for references. These scenarios include a description of the reference workloads that have been selected during the activity as representative for spacecraft applications. Lastly, the submission concept is introduced.

The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in$\mathbf{33D}$stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1)$\mathbf{100x}$performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2)$\mathbf{50x}$processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm2.

Artificial intelligence (AI) is paving the way for a new era of algorithms focusing directly on the information contained in the data, autonomously extracting relevant features for a given application. While the initial paradigm was to have these applications run by a server hosted processor, recent advances in microelectronics provide hardware accelerators with an efficient ratio between computation and energy consumption, enabling the implementation of AI algorithms “at the edge.” In this way only the meaningful and useful data are transmitted to the end-user, minimizing the required data bandwidth, and reducing the latency with respect to the cloud computing model. In recent years, European Space Agency (ESA) is promoting the development of disruptive innovative technologies on-board earth observation (EO) missions. In this field, the most advanced experiment to date is the$\Phi $-sat-1, which has demonstrated the potential of artificial intelligence (AI) as a reliable and accurate tool for cloud detection on-board a hyperspectral imaging mission. The activities involved included demonstrating the robustness of the Intel Movidius Myriad 2 hardware accelerator against ionizing radiation, developing a Cloudscout segmentation neural network (NN), run on Myriad 2, to identify, classify, and eventually discard on-board the cloudy images, and assessing the innovative Hyperscout-2 hyperspectral sensor. This mission represents the first official attempt to successfully run an AI deep convolutional NN (CNN) directly inferencing on a dedicated accelerator on-board a satellite, opening the way for a new era of discovery and commercial applications driven by the deployment of on-board AI.

The advent of powerful edge devices and AI algorithms has already revolutionized many terrestrial applications; however, for both technical and historical reasons, the space industry is still striving to adopt these key enabling technologies in new mission concepts. In this context, the current work evaluates an heterogeneous multi-core system-on-chip processor for use on-board future spacecraft to support novel, computationally demanding digital signal processors and AI functionalities. Given the importance of low power consumption in satellites, we consider the Intel Movidius Myriad2 system-on-chip and focus on SW development and performance aspects. We design a methodology and framework to accommodate efficient partitioning, mapping, parallelization, code optimization, and tuning of complex algorithms. Furthermore, we propose an avionics architecture combining this commercial off-the-shelf chip with a field programmable gate array device to facilitate, among others, interfacing with traditional space instruments via SpaceWire transcoding. We prototype our architecture in the lab targeting vision-based navigation tasks. We implement a representative computer vision pipeline to track the 6D pose of ENVISAT using megapixel images during hypothetical spacecraft proximity operations. Overall, we achieve 2.6 to 4.9 FPS with only 0.8 to 1.1 W on Myriad2 , i.e., 10-fold acceleration versus modern rad-hard processors. Based on the results, we assess various benefits of utilizing Myriad2 instead of conventional field programmable gate arrays and CPUs.