The chip industry is undergoing a market transition from mass production to mass customization. Rapid market changes require agile responses and diversified product designs, particularly in interface circuits managing chip-to-chip communication. To facilitate these shifts, this paper proposes a machine learning-based method for rapidly and accurately predicting and analyzing the performance of high-speed transceivers, along with an evaluation methodology utilizing the proposed approach. Especially, using the process technology information as input in the dataset, this is the first work to predict the performance of a design across different technologies, which will be invaluable in architecting and optimizing designs during the early stages of development. By simulating each functional block, we gather a dataset for parameterized design and performance and incorporate device characteristics from lookup tables. The transmitter, which operates like digital circuits, is trained using parameterized signals with a DNN, while the receiver, containing analog blocks and feedback structures, employs hybrid LSTM-DNN learning with time-series input and output. Our model, trained with a 40 nm design, demonstrates high accuracy in predicting performance even with different foundries and technologies. The majority of performance parameters show an R2value exceeding 0.9, indicating strong predictive accuracy under varying conditions. This method provides valuable insights for early-stage design optimization and process technology scaling, offering potential for broader applications in circuit design areas.

This paper presents a 56-Gb/s 3-tap feed-forward equalizer (FFE) four-level pulse-amplitude modulation (PAM-4) transmitter (TX) frontend for wireline applications. The proposed transmitter frontend operates at a 0.85-V termination voltage utilizing external surface-mounted (SMT) bias-tees. Unlike conventional tail-less current-mode logic (CML) drivers with variable gate biases, the transmitter frontend employs shunt-FFE for fewer variations in output common-mode levels. The design is fabricated in 40-nm CMOS technology and occupies 0.021 mm2. The proposed PAM-4 transmitter design operating at 56 Gb/s consumes 22.0 mW from 0.85-V supply voltage, achieving 0.39-pJ/bit energy efficiency.

In this paper, we introduce effective bus data en-coding schemes for next-generation interfaces of DRAM with an analysis of their energy and lane efficiency characteristics. The Pulse-Amplitude-Modulation-4 (PAM-4) signaling technique has recently been adopted to memory interfaces due to their increased per-pin data-rate requirements. However, as the power consumption profile of PAM-4 symbols differs from that of NRZ symbols, the conventional Dynamic Bus Inversion (DBI) encoding fails to achieve an expected reduction of termination power. Therefore, this paper proposes data encoding schemes applicable to the PAM-4 memory links and compares their performances in terms of the termination energy with experimental results. We evaluate the proposed approaches by applying data encoding to DRAM memory access traces obtained from executing benchmarks on ARM/x86 ISA-based processors, including caches, simulated on the gem5 architecture simulator. The experimental results show that our advanced encoding algorithms enable us to achieve doubled data rate with minimal power consumption overhead.