With the continuous scaling down of the feature size, the effect of shallow trench isolation (STI) on integrated circuit (IC) performance has become increasingly critical. This study pioneers the systematic investigation of oxide diffusion (OD) space effect (OSE) in 14nm fin field-effect transistor (FinFET) technology, proposing novel layout design strategies through isolation mode and structural optimizations to enhance digital unit performance. The results show significant performance improvements in specific digital units: AOI22V1 (72.33%), NAND3V1 (18.94%), MUX2V1 (13.96%), OAI211V1 (6.90%), OR3V2 (6.43%), and XNOR2V1 (6.41%). Alternating Current (AC) characterization reveals that replacing single diffusion breaks (SDB) with double diffusion breaks (DDB) in inverters improves operating frequency by 13% with a 10% dynamic power tradeoff. This work establishes OSE-aware layout design as an essential paradigm for FinFET optimization in advanced technology nodes.

Moore Law has met the limitation when since 2014, after moving to 16nm, so there are two research trends: More Moore and More than Moore. From an easy-to-implement point of view, 3D-IC is one good technology for More than Moore.

We propose a new technology and design platform using combined common gate (CG) N/PFET complementary field-effect transistor (CFET) as basic element for CMOS circuit applications. Two CFET unit structures, namely, CG and N-gate (NG), are identified to form base design elements. Through the two units, all circuit logic functions in standard cell library and SRAM can be realized without significant process complication. A multigradient neural network (MNN)-based SPICE compact modeling methodology is developed for these CFET units. As an example, MNN model generation is illustrated for CG with the output matching well with the TCAD data within and beyond the range of model extraction. Circuit simulations are exercised using the MNN models and demonstrated successfully the expected circuit functionalities. As the CFET technology be adopted as mainstream in future, this novel design framework proposed would enable efficient logic design.