Deep reinforcement learning (DRL) has emerged as a powerful tool for solving complex decision-making tasks in domains such as robotics, autonomous systems, and gaming. However, accelerating DRL on hardware platforms faces three major challenges: 1) large memory footprint of experience replay data; 2) inefficient weight access due to weight transposition; and 3) computational imbalance across processing elements during deep neural network (DNN) inference and training. To address these issues, we propose E2CAP, an energy-efficient field-programmable gate array (FPGA) accelerator tailored for DRL workloads. E2CAP integrates a compression strategy that significantly reduces the data volume of the experience pool in the DRL model, enabling on-chip deployment of the experience pool. In addition, E2CAP features a configurable array processing core (CAP) based on configurable processing elements (CPEs) that support both intra-PE and inter-PE configurability. This design effectively addresses the issues of weight trans position and computational imbalance, improving computational efficiency and hardware resources utilization. We implement full on-chip DRL inference and training using the DQN algorithm on E2CAP. Experimental results demonstrate a 98.19% compression ratio for experience replay data. Compared to the state-of-the-art CPU and GPU, E2CAP achieves$33.01\times $and$17.72\times $higher energy efficiency, respectively, while outperforming existing FPGA-based DRL accelerators in multidimensional performance.

Optical network-on-chip is a promising on-chip communication paradigm owing to higher bandwidth and lower latency. However, in the optical network, we have to consider the intrinsic characteristic of crosstalk noise, which has a significant impact on the overall performance of ONoC. In this paper, we proposed a low crosstalk and insertion loss 5×5 optical router called Srax with 15 microring resonators and 12 waveguide crossings, which has less microring resonators and waveguide crossings in comparison to other five-port router architectures. Experiments show that the Srax has lower insertion loss than Cygnus, Crossbar and Optical Router, which are 5.5%, 27.4% and 6.9% lower respectively. Similarly, Srax also has lower crosstalk compared to Cygnus and Optical Router, which are 1.0% and 4.3 % lower respectively.

In multiprocessor systems, low-latency synchronization is extremely important to effectively exploit fine-grain data parallelism and improve overall performance. This brief presents an efficient synchronization for embedded distributed multiprocessors. The proposed solution works in a completely decentralized request-response manner via explicit message exchange among the processing elements. Scalable lock and barrier synchronization algorithms, which are derived from the inherent distributed characteristics of the underlying architecture, are proposed to enable fair, orderly, and contention-free synchronization. We implement the proposed synchronization model in a distributed 32-core architecture with a commercial cycle-accurate SystemC simulation platform. Experimental results that show our proposed approach achieves ultralow synchronization latency and almost ideal scalability when the core count scales.

The breakdown of Dennard scaling prevents us from powering all transistors simultaneously, leaving a large fraction of dark silicon. This crisis has led to innovative work on power-efficient core and memory architecture designs. However, the research for addressing dark silicon challenges with network-on-chip (NoC), which is a major contributor to the total chip power consumption, is largely unexplored. In this paper, we comprehensively examine the network power consumers and the drawbacks of the conventional power-gating techniques. To overcome the dark silicon issue from the NoC's perspective, we propose DimNoC, a dim silicon scheme, which leverages recent drowsy SRAM design and spin-transfer torque RAM (STT-RAM) technology to replace pure SRAM-based NoC buffers. In particular, we propose two novel hybrid buffer architectures: 1) a hierarchical buffer architecture, which divides the input buffers into a set of levels with different power states and 2) a banked buffer architecture, which organizes the drowsy SRAM and the STT-RAM in different banks, and accesses them in an interleaved fashion to hide the long write latency of STT-RAM. In addition, our hybrid buffer design enables NoC data retention mechanism by storing packets in drowsy SRAM and nonvolatile STT-RAM in a lossless manner. Combined with flow control schemes, the NoC data retention mechanism can improve network performance and power simultaneously. Our experiments over real workloads show that DimNoC can achieve 30.9% network energy saving, 20.3% energy-delay product reduction, and 7.6% router area reduction compared with pure SRAM-based NoC design.

The diminishing momentum of Dennard scaling leads to the ever increasing power density of integrated circuits, and a decreasing portion of transistors on a chip that can be switched on simultaneously---a problem recently discovered and known as dark silicon. There has been innovative work to address the "dark silicon" problem in the fields of power-efficient core and cache system. However, dark silicon challenges with Network-on-Chip (NoC) are largely unexplored. To address this issue, we propose DimNoC, a "dim silicon" approach, which leverages drowsy SRAM and STT-RAM technologies to replace pure SRAM-based NoC buffers. Specifically, we propose two novel hybrid buffer architectures: 1) a Hierarchical Buffer (HB) architecture, which divides the input buffers into a hierarchy of levels with different memory technologies operating at various power states; 2) a Banked Buffer (BB) architecture, which organizes drowsy SRAM and STT-RAM into separate banks in order to hide the long write-latency of STT-RAM. Our experiments show that the proposed DimNoC can achieve 30.9% network energy saving, 20.3% energy-delay product (EDP) reduction, and 7.6% router area decrease compared with the baseline SRAM-based NoC design.