Electrostatic discharge (ESD) power clamps are critical for ensuring the reliability of modern integrated circuits (ICs). This paper presents an intelligent and automated design methodology that features application-driven topology selection tailored to diverse performance priorities and full-chain automation, from design specifications to silicon validation. The proposed approach begins with selecting representative circuit topologies, each tailored to specific application scenarios with distinct performance priorities. These topologies form a set of curated candidates defined by formalized design rules and established ESD protection principles. Subsequently, an optimization algorithm refines the dimensions of the device according to given specifications, while a professional floorplan and routing ensure high-current handling layout implementation. Compared with conventional manual design, the proposed methodology achieves superior design flexibility, comprehensive automation, and optimized performance, delivering balanced trade-offs among performance, power, and area (PPA). Post-layout simulations and silicon measurements in a 40-nm CMOS process validate the methodology, demonstrating the effectiveness of the intelligent algorithm in ESD protection design.

Since the data rates in advanced chips dramatically increase, the electrostatic-discharge (ESD) protection circuit at I/O ports causes significant ultrawideband challenges. To address these challenges, an arbitrarily tapped coil (AT-coil) structure with multitaps that enhance bandwidths is proposed; moreover, this structure can also fit into any rectangular layout area to save footprint. A microwave network-assisted analysis approach, which can better consider the nonideal factors in practical applications and thus converge to a better solution than traditional methods, is proposed with regard to the AT-coil. Further, machine learning-assisted optimization (MLAO) is introduced for the designing of AT-coil layouts for the first time, and prior human knowledge of high-speed circuits is maximally utilized to speed up MLAO processes. Thus, the converging stability is significantly improved to escape from a local optimum. Additionally, an automatic synthesis example for an on-chip spiral AT-coil proves the capability. Numerical results show that the proposed approach can achieve the best-high-frequency performance and guarantee ESD protective robustness.

An inductor is one of the basic passive circuit elements that make up integrated circuits. A hybrid knowledge-guided and data-driven technique (HKDT) that combines prior knowledge of on-chip inductors with a machine learning approach is proposed for designing a millimeter-wave on-chip deformable spiral inductor (DSI). First, a DSI, whose shape is no longer limited to a regular polygon and can be adapted to any rectangular region, is presented. Next, an expanded Wheeler formula is proposed to estimate the inductance of the DSI. Then, two approximate expressions with fitting parameters are deduced for the frequency responses of the inductance and quality factor. After that, two prior knowledge-guided Gaussian process regression (GPR) surrogate models are presented for the inductance and quality factor, with which the feature dimensions of the training data can be significantly reduced. Both models can achieve higher prediction accuracies in the frequency range of interest with lower computational complexity than the traditional GPR model with frequency-domain features when they are used for machine learning-assisted optimization (MLAO). Finally, an automatic inductor synthesis method is implemented by using a multibranch MLAO algorithm, and two examples are presented to validate the proposed synthesis method and illustrate its great capabilities. Ultimately, the HKDT can be extended to and applied for the efficient synthesis of other circuit elements with high accuracy.

This paper investigates the bigFET gate bias voltage in power-rail electrostatic discharge (ESD) clamp circuit for enhanced transient noise immunity. Based on a timed shutoff circuit, a resistor pair is employed to bias the bigFET gate voltage to different ratios of VDD. Through detailed investigations, an optimized bigFET gate bias scheme is proposed. With the optimized scheme, enhanced transient noise immunity of the investigated circuit is achieved. Besides, the optimized scheme can induce the channel and parasitic bipolar junction transistor parallel shunt paths in ESD events, which result in a lower on-resistance. Moreover, the optimized scheme is also validated in the high-threshold-voltage bigFET samples.

A power-rail electrostatic discharge clamp circuit with transient and static hybrid-detection enhanced triggering is proposed in this work. By skillfully co-optimizing the driving paths of both transient and static detection networks, the proposed circuit achieves a clamp device transient response time over 2 times longer than its RC time constant, which endows the proposed circuit with both promoted area-efficiency and safe clamping behaviors. Besides, the proposed circuit effectively combines the advantages of transient and static ones with tiny leakage current penalties. All investigated circuits are fabricated in a 65-nm CMOS process using 1.2-V thin-oxide devices. Simulation and test results are discussed in detail in this work to validate the proposed circuit.

This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved false-triggering immunity compared with the transient-triggered circuit. All investigated circuits are fabricated in a 65-nm CMOS process. Simulation and test results have both confirmed the superiority of the proposed circuit. In addition, the proposed circuit achieves similar triggering behaviors in both transmission line pulsing (TLP) and very fast TLP (VF-TLP) tests.