Continuous-Time Linear Equalizers (CTLEs) are typically deployed in a receiver for serial links applications, capable of compensating for channel attenuation by equalizing signal intensity across low- and high-frequency bands. Additionally, CTLEs have tunability for equalization to some extent to mitigate channel variations, offering a cost-effective solution for display applications that transmit signals with data rate of a few Gbps. To provide a survey study of CTLEs, this paper conducts a statistic survey of 83 prior works published by IEEE in the past 14 years comprising sixteen CTLE architectures. Among literature, five most used CTLE architectures, including source-degeneration, multi-path, negative-capacitance, active-inductor, and active shunt-shunt feedback CTLEs, are analyzed and compared with respect to peaking frequency, peaking gain, low frequency gain, eye height, eye width, linearity and noise. This comparison aims to provide a comprehensive study for circuit designers to select a suitable CTLE in pre-liminary design stage. In this work, experimental prototypes, including a source-degeneration and a multi-path CTLEs, are implemented in a 0.18-$\mu $m standard CMOS technology. The performance including eye height, eye width and power consumption are experimented in testing environment using a channel comprising a 600-mm flat flexible cable (FFC) and an 85-inch panel channel and input pattern generated by PRBS9.

The first 1.1V-programmable metal-fuse technology in 28nm CMOS technology is reported in this work. The prototyped 1Kb-memory array featuring a$12.4\mu $m2 1T1R bit cell adopts the proposed current-mode programming (CMP) scheme. The CMP scheme achieves a record low programming voltage of 1.1V, surpassing the programming voltages (≥1.6V) required by prior metal-fuse CMOS and FinFET technologies. To ensure successful programming, a closed-loop detector (CLD) employing an on-chip hysteresis comparator detects resistance transition in bit cells during programming. Preliminary experiments demonstrate that the proposed CMP scheme along with CLD achieves a 100% of yield after programming 960 bits at room temperature. Under various programming conditions, the combination of CMP and CLD demonstrates programming robustness, with resistance ratios before and after programming equal to and greater than three orders of magnitude. The measured results suggest a promising method for mitigating over-stress issues associated with high programming voltages used in prior art.

The first 36-Gb/s transmitter with differential outputs leveraging the three-level pulse amplitude modulation (PAM-3) and digital logic cells is investigated in this study. The employment of digital logic cells simplifies design complexity, enabling the transmitter to achieve an energy efficiency of 1.6pJ/bit under a 1-V supply, and 0.88 pJ/bit when solely considering the data path. The measurement of data rates and energy efficiencies is conducted using an external power supply, omitting an on-chip voltage regulator. The proposed transmitter adopts a 3-bit to 2 unit-intervals (UIs) encoding scheme, considering factors of power consumption, design complexity, area, and bit efficiency. The circuit macro is fabricated in 22nm standard CMOS technology and occupies an area of 0.025mm2 for the transmitter only, and 0.055mm2 for both the transmitter and T-coils. The utilization of 4-tap feedforward equalizer (FFE) yields enhancement in eye opening area, achieving a substantial 96.5% increase at 33Gb/s of data rate and 300% at 34.5Gb/s. The eye measurements are conducted using a pair of 0.914-meter cables.

This paper presents a low-input-voltage (100 mV), low-output-voltage (500-600 mV) thermoelectric energy harvesting interface circuit for near-threshold energy-efficient Internet-of-Things (IoT) devices. The capacitive bootstrapping technique is used to generate a positive and negative bias pair for alleviating the significant conduction losses of power MOSFETs in a near-threshold operation. Internal bias voltages are automatically boosted to different levels as per the loading conditions to extend the output power range. The deployment of constant on-time digital pulse skip modulation with digital zero current detection (ZCD) achieves an ultralight load operation, and precluding a reverse current. The digital ZCD is capable of dynamically adjusting the off-time (TOFF) of the power transistors, which vary according to the input and output voltage levels. The proposed step-up dc-dc power converter implemented using a 180 nm CMOS technology demonstrates a maximum conversion efficiency of 76.4% over a 1 μW-500 μW load range, significantly evaluating the feasibility of the near-threshold interface circuit architecture for energy-efficient IoT devices.