Recurrent neural networks (RNNs) are used extensively in time series data applications. Modern RNNs consist of three layer types: recurrent, Fully-Connected (FC), and attention. This paper introduces the design, acceleration, implementation, and verification of a complete reconfigurable RNN using a system-on-chip approach on an FPGA. This design is suitable for small-scale projects and Internet of Things (IoT) end devices as the design utilizes a small number of hardware resources compared to previous configurable architectures. The proposed reconfigurable architecture consists of three layers. The first layer is a Python software layer that contains a function serving as the architecture’s user interface. The output of the python function is three binary files containing the RNN architecture description and trained parameters. The embedded software layer implemented on an on-chip ARM microcontroller is the second layer of that architecture. This layer reads the first layer output files and configures the hardware layer with the required configuration and parameters to execute each layer in the RNN. The hardware layer consists of two Intellectual Properties (IPs) with different configurations. The Recurrent Layer Hardware IP implements the recurrent layer using either Long Short Term Memory (LSTM) or Gated Recurrent Unit (GRU) as basic building blocks, while the ATTENTION/FC IP implements the attention layer and the FC layer. The proposed design allows the implementation of a recurrent layer on an FPGA with variable input and a hidden vector length of up to 100 elements for each vector. It also supports implementing an attention layer with up to 64 input vectors and a maximum vector length of 100 items. The FC layers can be configured to support a maximum value of 256 for the input vector length and the number of neurons in each layer. The hardware design of the recurrent layer achieves a maximum performance of 1.958 and 2.479 GOPS for the GRU and LSTM models, respectively. The maximum performance of the attention and FC layers is 2.641 GOPS and 634.3 MOPS, respectively. The hardware design works at a maximum frequency of 100 MHz.

Data classification has improved significantly over time and nowadays is used in a variety of purposes and applications. This paper demonstrates the design and implementation of multivariate classifier linear discriminant algorithm on a Field Programable Gate Array (FPGA) as System on Chip (SoC). The classifier is optimized using High Level Synthesis (HLS) techniques. The optimized design is placed on the programmable logic part of the chip while its controller is built on the embedded processor of the same chip. The paper details the process of the classifier design and optimization and reports on the power consumption, resource utilization, latency, and algorithm accuracy before and after optimization.

Speech recognition has seen dramatic improvements in the last decade, though those improvements have focused primarily on adult speech. In this paper, we assess child-directed speech recognition and leverage a transfer learning approach to improve child-directed speech recognition by training the recent DeepSpeech2 model on adult data, then apply additional tuning to varied amounts of child speech data. We evaluate our model using the CMU Kids dataset as well as our own recordings of child-directed prompts. The results from our experiment show that even a small amount of child audio data improves significantly over a baseline of adult-only or child-only trained models. We report a final general Word-Error-Rate of 29% over a baseline of 62% that uses the adult-trained model. Our analyses show that our model adapts quickly using a small amount of data and that the general child model works better than school grade-specific models. We make available our trained model and our data collection tool.

Network-on-Chip (NoC) has become exposed to security threats. It can be infected with a Hardware Trojan (HT) to degrade the system performance and apply a denial of service attack. In this paper, we proposed a new HT-based threat model, known as Black Hole Router (BHR), where it deliberately drops packets from the NoC. We proposed a detection and prevention protocol to such BHR attack with reasonably low overhead. The results show 10.83%, 27.78%, and 21.31% overhead in area, power, and performance, respectively. However, our proposed protocol not only detects the BHR attack but also avoids it and assures packet-delivery.

Scale Invariant Feature Transform (SIFT) algorithm is one of the classical feature extraction algorithms that is well known in Computer Vision. It consists of two stages: keypoint descriptor extraction and descriptor matching. SIFT descriptor matching algorithm is a computational intensive process. In this work, we present a design and implementation of a hardware core accelerator for the descriptor-matching algorithm on a field programmable gate array (FPGA). Our proposed hardware core architecture is able to cope with the memory bandwidth and hit the roofline performance model to achieve maximum throughput. The matching-core was implemented using Xilinx Vivado® EDA design suite on a Zynq®-based FPGA Development board. The proposed matching-core architecture is fully pipelined for 16-bit fixed-point operations and consists of five main submodules designed in Verilog, High Level Synthesis, and System Generator. The area resources were significantly reduced compared to the most recent matching-core implemented on hardware. While our proposed hardware accelerator matching-core was able to detect 98% matching-points compared to the software approach, it is 15.7 × faster.

This paper presents a novel cell architecture for evolvable systolic arrays. HexCell is a tile-able processing element with a hexagonal shape that can be implemented and dynamically reconfigured on field-programmable gate arrays (FPGAs). The cell contains a functional unit, three input ports, and three output ports. It supports two concurrent configuration schemes: dynamic partial reconfiguration (DPR), where the functional unit is partially reconfigured at run time, and virtual reconfiguration circuit (VRC), where the cell output port bypasses one of the input data or selects the functional unit output. Hence, HexCell combines the merits of DPR and VRC including resource-awareness, reconfiguration speed and routing flexibility. In addition, the cell structure supports pipelining and data synchronization for achieving high throughput for data-intensive applications like image processing. A HexCell is represented by a binary string (chromosome) that encodes the cell's function and the output selections. Our developed evolvable HexCell array supports more inputs and outputs, a variety of possible datapaths, and has faster reconfiguration, compared to the state-of-the-art systolic array while maintaining the same resource utilization. Moreover, by using the same genetic algorithm on the two systolic arrays, results show that the HexCell array has higher throughput and can evolve faster than state-of-the-art array.

This paper presents an optimized fixed-point implementation of space-vector pulse-width modulation (SVPWM) for a two-level inverter. Bit-width fixed-point signals as well as circuit area are minimized by meeting the desired design accuracy. Most of the designs currently available are specified in floating-point precision to speed the process of simulating their functionality. However, area-optimized hardware implementation of these algorithms requires fixed-point precision. A generic function is used to formulate the precision required for each signal to get the proper accuracy. A non-convex optimization problem is solved for the number of required bit-widths for the signals. This solution has been simulated and implemented on FPGA to verify the resulting accuracy.