Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Xianjian Zheng

dblp:158/8116 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 67% Electronic design automation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA testing		 0.212015
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only) · FPGA 2015
Electronic design automation
hardware verification and test		 0.212015
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only) · FPGA 2015
Reconfigurable computing and FPGAs › dynamic reconfiguration
partial reconfiguration		 0.212015
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only) · FPGA 2015

Methods — techniques the papers use, named apart from their topics

sorting algorithms · 0.2partial reconfiguration · 0.2
YearPublicationVenuePosition
2015 A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only)
abstract
The programmability of an FPGA poses a number of challenges when it comes to complete and comprehensive testing of the FPGA itself. A large number of configurations must be downloaded into the FPGA to test the programmable sources. A great many methods were proposed to reduce the number of configurations to minimize the test time, but few of papers were focus on reducing single configuration time. This paper proposes a novel method to reduce more than 30% of the total configuration time based on partial reconfiguration technology and sorting algorithm. This method is implemented on a series of SRAM-based FPGAs. The experimental result shows that this method reduces 30%-45% of the total configuration time and can be generally applied to all SRAM-based FPGAs currently.
Xianjian Zheng, Lei Chen 0010, Zhiping Wen 0001, Yuanfu Zhao, Xuewu Li
 FPGA1