In the chiplet-based chip, multiple dies are communicated through a large amount of inter-die interconnects. The bonding interfaces, e.g., microbumps (ubumps), of the interdie interconnects are prone to defects during the assembly process. Effective yield-enhancement techniques for inter-die interconnects thus are needed to ensure the yield of chiplet-based ICs. In this paper, we propose a fault-aware repair technique for inter-die interconnects. A test and diagnosis method is proposed to distinguish single-net faults from multi-net faults and identify the interconnects of a multi-net fault. Then, a shift and broadcast reconfiguration method is used to repair two interconnects with a short defect using one spare interconnect. Simulation and analysis results show that the proposed fault-aware repair technique can effectively increase the repair rate.

To overcome the von Neumann bottleneck, computing-in-memories (CIMs) have emerged as a design trend. On the other hand, with the globalization of the semiconductor supply chain, hardware Trojans have become a significant security concern. While there have been some studies on hardware Trojan designs for embedded memories in the past, there is no literature addressing hardware Trojan designs for CIMs. In this article, we propose a hardware Trojan design for spin transfer torque magnetoresistive random access memory (STT-MRAM)-based CIMs that can disrupt computing-mode operations. Our trigger circuit can evade detection during post-manufacturing memory testing, and our payload circuit can disrupt over 99% of CIM operations. Experimental results also demonstrate that compared to the original peripheral circuits of STT-MRAM-based CIMs, the area overhead and power overhead (at the TT process corner) caused by our inserted hardware Trojan are only 1.023% and 0.123%, respectively. Therefore, our hardware Trojan can easily hide within the peripheral circuits.

Spin-transfer-torque magnetic random access memory (STT-MRAM) is a candidate for next-generation memory to cope with scaling challenges of conventional memories. However, the STT-MRAM has a small on/off resistance ratio which poses challenges in designing the reference resistance. An effective approach to cope with this issue is to design a trimmable reference resistance that allows post-production control of the reference resistance. A trimming test should be used in the production test to find an appropriate reference resistance. In this paper, a parallel-check trimming test (PCTT) approach aimed at significantly reducing the trimming test time is proposed. In comparison with the existing binary-judge-based search test approach, the proposed PCTT approach drastically reduces trimming test time with nearly the same read yield.

Various advanced packaging technologies have been proposed to integrate multiple dies into a package. In the multidie package, a significant amount of inter-die interconnects are used to assemble the dies. The bonding interfaces, e.g., microbumps (ubumps), of the inter-die interconnects are prone to defects during the assembly process. Therefore, it is crucial to test the inter-die interconnects to ensure the quality of the assembly. In this paper, we propose an efficient built-in self-test (BIST) scheme for the testing of inter-die interconnects of chiplet-based ICs. The transmitters/receivers under test are logically arranged as a 2D array. A test algorithm that utilizes alternating row stripe and column stripe test patterns is proposed. These 2D test patterns are then compressed into 1D test patterns such that the test application time can be reduced. Simulation and analysis results show that the proposed BIST scheme can achieve 99.9% test time reduction and save about 53.5% area cost for a 32×64 ubump array in comparison with a typical test scheme, IEEE 1500 test scheme.

Spin-transfer-torque magnetic random-access memory (STT-MRAM) is one of the most promising emerging memories for on-chip memory. However, the magnetic tunnel junction (MTJ) in the STT-MRAM suffers from several reliability threats which degrade the endurance, create defects, and cause memory failure. One of the primary reliability issues comes from time-dependent dielectric breakdown (TDDB) on MTJ, which deviates resistance value of MTJ over time and may lead to reading error. To overcome this challenge, in this paper we present an on-line aging detection and tolerance framework to dynamically monitor the electrical parameter deviations and provide appropriate compensation to avoid reading error. The on-line aging detection mechanism can identify aged words by monitoring read current and then the aging tolerance mechanism can adjust the reference resistance of the sensing amplifier to compensate the aging-induced resistance drop of MTJ. In comparison with existing testing-based aging detection techniques, our mechanism can operate on-line with read operations for both aging detection and tolerance simultaneously with negligible performance overhead. Simulation and analysis results show that the proposed techniques can successfully detect 99% aging words under process variation and achieve at most 25% reliability improvement of STT-MRAMs.

Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

Welcome to the 31th Asian Test Symposium (ATS 2022). Since 1992, ATS has been held every year in various Asian cities as the largest symposium that focuses on testing of integrated circuits and systems. Many researchers and engineers from all over the world have attended the past symposia and enjoyed discussions. After more than two years of COVID-19 pandemic, ATS 2022 is being held as a hybrid event to invite symposium participants to join on-site meeting, and also to allow on-line participation through conference app platform.

Various computing-in-memory designs have been proposed as a possible computing architecture for the data-centric computing applications. Existing memories such as random access memories, flash memories, and emerging memories can be modified as computing-in-memories (CIMs) to support computing operations. In CIMs, computing operations typically are more complex and have smaller sensing margin than the read operation. Furthermore, storage devices of emerging memories are more unreliable than transistors. Those make the testing and reliability of CIMs become worse. In this paper, we first review existing testing and reliability-enhancement methods for CIMs. Then, testing and reliability challenges of CIMs are discussed.

Resistive random access memory (RRAM) is one promising nonvolatile memory. It also is a good candidate for realizing computing-in memories. In this paper, we perform fault modeling for 1T1R RRAM-based computing-in memories (CIMs). Although there are existing works reported fault modeling and testing for RRAMs and RRAM-based CIMs, they do the fault analysis based on bit-oriented array organization. Here we inject intra-cell and inter-cell electrical defects in a word-oriented cell array for the fault analysis. Fault analysis results show that a RRAM-based CIM may have computing faults and data dependent faults in addition to conventional RRAM faults. We also propose a march test March-R11N for the 1T1R RRAM-based CIMs. Analysis results show that March-R11N requires 11N test complexity to cover all the typical faults and defined faults of a 1T1R RRAM-based CIM with$N$words.

Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is one promising nonvolatile memory. In this paper, a design-for-testability (DFT)-enhanced test scheme is proposed to enhance the test quality of STT-MRAMs by adaptively adjusting the read current of the read test operations using a read current-adjustable DFT (RCA-DFT) circuit. A march test, March-MT, is proposed as well. Together with RCA-DFT, March-MT requires$11N$test complexity to achieve about 7.26 times of total test quality improvement in comparison with a March-6N test algorithm with fixed read current for a STT-MRAM with$N$words.

In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Various IMC memories using 8T static random access memory (SRAM) cell have been reported. Some of them, the memory array can provide SRAM and ternary content addressable memory (TCAM) function. In this paper, a March-like test algorithm is proposed, which requires 10 × 2pRead/Write operations, (2q+ 4m) Compare operation, and (2r+1+ 4m) Erase operations to cover simple SRAM faults and TCAM Comparison faults, for an IMC 8T SRAM providing 2p×w-bit SRAM and m× 2q−1-bit TCAM, where p = q+r and m = 2r×w.

A deep neural network (DNN) system typically needs dynamic random access memories (DRAMs) for the data buffering. In this paper, an error-correction-code (ECC)-based technique is proposed to reduce the refresh power of DRAMs in the DNN system by extending the refresh period. By taking advantage of the characteristics of weight data of DNNs, a hybrid voting and ECC (VECC) method is used to protect the weight data from data retention fault caused by the refresh period extension. Analysis results show that the VECC method can achieve about 93% refresh power saving with about 0.5% accuracy loss and smaller than 0.5% check bit overhead on AlexNet, ResNet, and VGG19 convolutional neural network CNN models trained by ImageNet data set.

Content addressable memory (CAM) is widely used in the systems with the need of parallel search. The testing of CAM is more difficult than that of random access memory (RAM) due to the complicated function of CAM. Similar to the testing of RAM, the testing of CAM should cover the cell array and peripheral circuits. In this paper, we propose a March-like test, March-PCL, for detecting the stuck-open faults (SOFs) of the priority address encoder of CAMs. As the best of our knowledge, this is the first word to discuss the testing of SOFs of the priority address encoder of CAMs. The March-PCL requires 4N Write and 4N Compare operations to cover 100% SOFs.

Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

Ternary content addressable memory (TCAM) is widely used for the network applications. However, TCAM is a power- and area-consuming component. Memristor-based TCAM is considered as a good alternative for reducing the required power and area. In this paper, we define comparison faults of 5T2R memristor-based TCAMs. Electrical defects such as transistor stuck-open/stuck-on, resistive open, short, and bridge are comprehensively injected and simulated by Hspice. We also propose a March-like test March-MCAM to fully cover the defined comparison faults. March-MCAM requires 6N Write operations and (14N + 2B) Compare operations for an N × B-bit mrTCAM.

A DRAM with multiple-refresh-period (MRP) method is one of effective refresh power reduction techniques. To support the MRP method, effective test methods for classifying the refresh period of each DRAM block are needed. In this paper, we propose an effective test method for classifying the refresh periods of DRAM blocks. Also, a programmable built-in self-test (BIST) scheme being able to support the test method is proposed.

Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array testing. Thus, it is inefficient to realize it using the dedicated BIST hardware. On the other hand, it is not time efficient if we use the processor (software) to execute the DRAM array testing. Therefore, the SHC-BIST scheme uses a programmable BIST circuit to execute the DRAM array testing and takes advantage of the processor to execute the DRAM initialization and control the programmable BIST circuit such that the test time and hardware cost can be minimized. We verify the SHC-BIST scheme using a system with a LEON3 processor and a multi-channel DRAM.

Memristor is a resistive device which is considered as an alternative non-volatile device for future non-volatile memories. For a memristor memory, a reference current is needed for discriminating the high-resistance (ROFF) state from low-resistance (RON) state. The reference current has an impact on the yield and reliability of the memristor memory. In this paper, we propose a test method in associate with a current comparing circuit for finding the boundary currents of ROFF and RON states. Therefore, the user can set a good reference current according to the boundary currents. Simulation results show that if our test method is used to identify the boundary currents, 2.05% and 3.68% memristor cells which may be read incorrectly due to process variation for ROFF/RON = 50 and 3 can be eliminated, respectively.

This paper proposes a built-in delay measurement (BIDM) technique to measure the delay of through-silicon via (TSV) in the phase of post-bond test. The BIDM circuit can be shared by multiple TSVs such that the area overhead of the BIDM circuit is minimized. Furthermore, a measurement flow is proposed to eliminate the delay of interconnection between two TSVs such that the BIDM accuracy is not worsened with the increased number of measured TSVs. Experimental results show that the deviation of the result of BIDM and Hspice simulation is about 2.7%. Furthermore, a low-cost delay measurement element is proposed. In comparison with a typical Vernier delay line, the proposed delay measurement element can achieve 18% area reduction. In comparison with the ring-oscillator-based delay measurement method, the proposed BIDM has the features of low error and low cost, but needs long measurement time.

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast poweron speed. A Rnv8T SRAM cell is composed of a 6T SRAM cell, two resistive devices, and two transistors. In this paper, we define several memristor-related faults for the Rnv8T SRAM considering electrical defects. Also, a March-like test algorithm which can cover simple SRAM faults and defined memristor-related faults are proposed. In comparison with the existing work, the proposed March-like test needs longer test time, but provides better fault coverage on the targeted faults.

Wide-I/O dynamic random access memory (wide I/O DRAM) is one of promising solutions to increase the memory bandwidth. Similar to modern double-data-rate DRAMs, the minimum burst length of wide I/O DRAM is at least two. Thus, either a read or a write operation is executed, two words will be read or written at least each time. This causes that the testing of inter-word coupling faults becomes complicated. In this paper, we propose a method to modify conventional March tests into modified March tests which can fully cover inter-word coupling faults of wide I/O DRAMs with minimum burst length of two and programmable burst order. Furthermore, the test complexity of modified March tests for different burst lengths is analyzed. Results show that the test time of modified March tests is the shortest if the longest burst length is set to apply the modified March tests. Results of fault coverage analysis show that the modified March test can provide 100% fault coverage of simple inter-word coupling faults.

Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.

A built-in self-repair (BISR) scheme for random access memories (RAMs) with 2-D redundancy has a built-in redundancy analyzer (BIRA) for allocating the redundancy. The BIRA typically has a cache-like element called local bitmap for storing the fault information temporary. In this paper, a high-repair-efficiency BISR (HRE-BISR) scheme for RAMs is proposed. The HRE-BISR reuses the local bitmap to serve as spare bits such that it can repair more faults. In addition, a row/column/bit redundancy analysis (RCB-RA) algorithm for a RAM with spare rows, spare columns, and spare bits is presented. Simulation results show that the proposed HRE-BISR scheme can provide higher repair rate (RR) than a typical BISR scheme without reusing the local bitmap as spare bits. Only about 0.44% additional hardware overhead is needed to modify the local bitmap as spare bits. In addition, the HRE-BISR scheme using 3 × 3-bit local bitmap for RA only incurs about 0.08-ns delay penalty for a 512 × 16 × 32-bit RAM with one spare row and one spare column. However, the HRE-BIRA scheme with RCB-RA algorithm can provide 0.48%-11.95% increment of RR for different fault distributions.

An non-volatile logic (NVL) -based system chip uses non-volatile storage elements to backup working state of volatile storage elements in sleep mode such that the power of chip can be turned off and zero standby power can be achieved. Since an NVL-based system chip consists of logic circuits and non-volatile storage elements, tests for logic circuits only and for non-volatile memories only are not sufficient for the testing of NVL-based system chips. The interface circuit between the volatile storage element and the non-volatile storage element must be tested as well. This paper presents possible faults occurred in the NVL-based system chips when the backup and restore operations are executed. Then, an effective test method with alternating 0/1 test sequence for detecting the defined backup and restore faults is proposed. In comparison with a straightforward test method, the proposed test method can achieve 41% test time reduction for an NVL-based design with 2537 flip flops.

Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.

Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 -- 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.

Contests and their benchmarks have become an important driving force to push our EDA domain forward in different areas lately, such as ISPD, TAU, DAC contests. The annual CAD Contest in Taiwan has been held for 14 consecutive years and has successfully boosted the EDA research momentum in Taiwan. To encourage better research development on timely and practical EDA problems across all domains, CAD Contest is internationalized since 2012 under the joint sponsorship of the IEEE CEDA and Ministry of Education (MOE) of Taiwan. 2012 CAD Contest attracted 56 teams from 7 regions, while 2013 CAD contest attracted 87 teams from 9 regions. Continuing its great success in 2012 and 2013, 2014 CAD contest attracts 93 teams from 9 regions, including Taiwan, Mainland China, Hong Kong, India, Singapore, US, Canada, Brazil, and Russian Federation. Three contest problems on verification, placement, and mask optimization are announced this year and run by industry experts from Cadence and IBM. Topic chair Chih-Jen Hsu of Cadence Design Systems manages the first contest problem, concentrating on efficiently solving the combinational single-output netlists. The efficiency of solving a single-output function highly depends on the CNF encoding and the SAT solving. For the first problem, contestants are required to explore the best CNF encoding and SAT solver setting to solve the most tests within the shortest runtime. Topic chair Myung-Chul Kim of IBM manages the second problem, focusing on incremental timing-driven placement. Placement, which determines locations of circuit elements, is one of the most crucial steps in the modern IC design flow. For the second problem, contestants are required to perform local refinements on a legal design such that the total slack and worst slack are optimized. Topic chair Rasit O. Topaloglu of IBM manages the third problem, exploring lithography mask optimization. In a circuit layout, densities of polygons within windows of interest may have a large variation across such windows in the rest of the layout. To balance the density of polygons, fills are inserted to make the density of several windows uniform. For the third problem, contestants are required to minimize the density variation with least fills. This session will include three presentations from the contest organizers for these contest problems and an award ceremony. Each contest organizer (topic chair) will present detailed information about the corresponding contest problem, including problem description, benchmarks, and evaluation. Along with the contest, a new set of industrial benchmarks for each contest problem will be released and facilitate scientific evaluations of related research results. We expect that the benchmark suites will further play a key driving force to push the advancement of related research. Moreover, we also expect that the participants will submit their works to the subsequent top conferences to boost related research and also extend the impacts of this contest.

This paper proposes a built-in self-test (BIST) scheme with syndrome-compression ability for random access memories (RAMs) with static (SF) and dynamic faults (DFs). A March-element-based (MEB) compression scheme is proposed to reduce the volume of diagnostic data. The MEB compression scheme can efficiently compress the diagnostic data of a RAM tested by a March test for detecting SFs and DFs. Simulation results show that the compression ratio (the ratio of the number bits of the compressed diagnostic data to that of the original diagnostic data) is about 50.79% for an 8K×16-bit memory. The area overhead of the BIST with the MEB compressor is about 2.73% for an 8K×16-bit RAM using TSMC 0.18 um cell library.

A three-dimensional (3D) integrated circuit (IC) with multiple dies vertically connected by through-silicon-via (TSV) offers many benefits over current 2D ICs. Multicore logic-memory die stacking has been considered as one candidate for 3D ICs by utilizing the TSV to provide high data bandwidth between logic and memory. However, 3D ICs suffer from the low-yield issue. This article proposes effective yield-enhancement techniques for multicore die-stacked 3D ICs. Two reconfiguration schemes are proposed to logically swap the positions of cores in the dies of 3D ICs such that the yield of 3D ICs is increased. Two algorithms also are proposed to determine the reconfiguration effectively. Simulation results show that the proposed reconfiguration schemes can achieve a yield gain ranging from 1% to 11%.

NAND flash memory is the most popular nonvolatile memory. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot, some NAND flash memories with single-page word lines and some with multiple-page word lines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are developed.

Three-dimensional (3-D) integration technology using through-silicon via (TSV) is an emerging integrated-circuit (IC) design technology. In this paper, we propose a repair scheme to enhance the yield of TSVs in 3-D ICs. The proposed TSV repair scheme uses an enhanced test access architecture to alleviate the requirement of additional repair registers such that the area cost can be drastically reduced. In comparison with existing scan-based test and repair approaches, simulation and analysis results show that the proposed TSV repair scheme can provide the best final yield and consume the smallest area cost for 128 TSVs with one spare TSV. On the other hand, the proposed repair schemes with 1149.1-based and 1500-based wrapper cells for 128 TSVs only need 12% and 20% additional area cost in comparison with the 1149.1 and 1500 test access architectures.

A modern system-on-chip (SOC) may become one of the dies of a three-dimensional (3D) IC using through-silicon via (TSV). Built-in self-repair (BISR) techniques have been widely used to improve the yield of RAMs in a SOC. This paper proposes a memory BISR allocation scheme to allocate shared BISR circuits for RAMs in a SOC die such that the test and repair time and the area of BISR circuits are minimized. To minimize the test and repair time of RAMs in the pre-bond and post-bond test phases, a test scheduling engine is used to determine the pre-bond and post-bond test sequences of RAMs under the corresponding test power constraints. Then, a BISR-circuit minimization algorithm is proposed to reduce the number of required shared BISR circuits for the RAMs under the constraints of pre-bond and post-bond test sequences and distance between the BISR circuit and served RAMs. Simulation results show that in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit), 35% area reduction can be achieved by the shared BISR scheme planned by the proposed allocation technique under lmm distance constraint, and 500mW and 600mW pre-bond and post-bond test power constraints, respectively.

Three-dimensional (3D) integration using through silicon via (TSV) is a promising approach to coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented by stacking multiple dies which are vertically connected by TSVs. This may shorten the global interconnects of a 3D IC and greatly improve its performance and power consumption. High bandwidth is achieved by the increase of IO channels provided by the TSVs, which also reduce the unnecessary waste of energy during data movement. In addition, the 3D integration technology shows other advantages over 2D technology, such as high functionality, heterogeneous integration, small form factor, etc. However, there are still challenges that need to be tackled before volume production of 3D ICs using TSV becomes possible, including technology scalability, quality and reliability, yield, thermal management, equipment and infrastructure, and costs. To demonstrate the feasibility of 3D-IC technologies, many academic and industrial institutes have been working on various test vehicles, especially in recent years. An increasing attention also has been attracted around the world in the semiconductor industry by the development of related technologies. In this special session, we will discuss the evolutionary efforts toward the realization of 3-D ICs. As memory dies need to be integrated in most 3D-IC system, we will also address the challenges in the design and test of 3D memories against cross-layer process, voltage and temperature variations while suppressing thermal effect and power consumption, etc. We will share our experiences and show results from some of the test vehicles we have worked on, including processor/memory stacks, analog/logic stacks, logic/logic stacks, etc. We will show a 1,024-bit wide bus chip-to-chip interconnection using 40×40 fine-pitch TSVs to demonstrate ultra-low-power operation. For memories, we will present a 3D-RAM structure using small voltage-swing TSVs, vertical-device-stacking nonvolatile-SRAM and ReRAM, and a 3D vertical-gate NAND flash. To address the challenge of reliability and yield, we will also discuss important test techniques. Demonstration of benefits provided by 3D integration technology will also be shown. Last but not least, we will describe our development plan regarding various types of die stacking using heterogeneous process integration, especially processor/memory stacking that is widely believed to be a key technology in future generations of smart handheld devices.

Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40~70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

The three-dimensional (3D) random access memory (RAM) using through-silicon via (TSV) has been considered as a promising approach to overcome the memory wall. However, cost and yield are two key issues for volume production of 3D RAMs, and yield enhancement increasingly requires test techniques. In this paper, we first introduce issues and existing techniques for the testing and yield enhancement of 3D RAMs. Then, a built-in self-repair (BISR) technique for 3D RAM using global redundancy is presented. According to the redundancy analysis results of each die with the BISR circuit, the die-to-die (d2d) and wafer-to-wafer (w2w) stacking problems are transferred to the bipartite maximal matching problem. Then, heuristic algorithms are also proposed to optimize the stacking yield.

Summary form only given. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. In this paper, therefore, test algorithms for covering the disturbance faults in various types of NAND flash memories are developed.

Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization mechanism is also proposed to synchronize the BIST circuits in different dies. Furthermore, the BIST circuit provides the high-programmability feature to support the selection of RAMs in a die for testing such that it can support thermal management during the test. We design the proposed BIST scheme in a 3D IC with processor and RAM dies. Experimental results show that the area cost of the BIST circuit is very small. The area overhead of the BIST circuit for four 8192×64-bit RAMs in a die is only 0.45% using TSMC 90nm 1P9M CMOS process technology.

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

Ternary content addressable memory (TCAM) is a key component in various digital systems due to its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fault models of TCAMs with asymmetric cells based on electrical defects. Some new comparison faults which do not exist in a TCAM with symmetric cells are found. One march-like test algorithm TAC-His also proposed to cover the defined comparison faults. The TAC-Hconsists of 8N Write operations and (3N + 2B) Compare operations for an N × B-bit TCAM with Hit output only. We also propose two march-like diagnosis algorithms to identify the defined comparison faults of TCAMs with asymmetric cells. The first diagnosis algorithm DAC-Hrequires 5N Write operations, 3N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit output only. The second diagnosis algorithm DAC-Prequires 3N Write operations, 1N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit and priority address encoder outputs.

Built-in self-repair (BISR) techniques are widely used for the repair of embedded memories. One of the key components of a BISR circuit is the built-in redundancy-analysis (BIRA) module, which allocates redundancies according to the designed redundancy analysis algorithm. Thus, the BIRA module affects the repair rate of the BISR circuit. Existing BIRA schemes for RAMs can provide the optimal repair rate (the ratio of the number of repaired RAMs to the number of defective RAMs), but they require either high area cost or multiple test runs. This paper proposes a BIRA scheme for RAMs, which can provide the optimal repair rate using very low area cost and single test run. Furthermore, the BIRA is designed as reconfigurable such that it can be shared by multiple RAMs. Experimental results show that the area cost for implementing the proposed BIRA scheme is much lower than that of existing BIRA schemes with optimal repair rate. A test chip is also implemented to demonstrate the proposed BIRA scheme.

3-D integration using through-silicon-via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. Test and yield are two big issues for volume production of 3-D ICs. In this paper, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3-D ICs. The BISR scheme, arranging the TSVs into arrays similar to memories, can effectively enhance the yield of TSVs in a 3-D IC such that the yield of the 3-D IC is boosted. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3-D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.

This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing the enhanced IEEE 1500 test wrapper is only about 0.58% for a 64 K-bit single-port RAM and only 0.57% for a 64 K-bit two-port RAM in 90-nm technology.

This paper proposes a Pai-Sigma matchline scheme to reduce the compare (search) power of a ternary content addressable memory (TCAM). The proposed matchline does not incur the issues of charge sharing and short circuit current, which typically exist in the hybrid nand-nor matchline. Moreover, the switching activity of the search lines of a TCAM with the proposed matchlines is low. A 32×64-bit TCAM with the Pai-Sigma matchlines is implemented to demonstrate the low-power feature. Results show that the compare power of the TCAM can achieve 60% energy reduction compared with the conventional nor-type TCAM. Also, the energy consumption per bit per search of the TCAM is only 2.287 fJ/bit/search.

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18μm CMOS technology for a 16×32 TSV array in which each TSV cell size is 45μm2is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.

Built-in self-repair (BISR) techniques are widely used to enhance the yield of random access memories (RAMs) in a system-on-chip (SoC) which typically consists of hundreds of RAMs. Hence, many BISR circuits may be needed in a such SoC. Effective techniques for planning these BISR circuits thus are imperative. In this paper, we propose a memory BISR planning (MBiP) framework for the RAMs in SoCs. The MBiP framework consists of a memory grouping algorithm for selecting RAMs which can share a BISR circuit. Then, a test scheduling algorithm is used to determine the test sequence of RAMs in a SoC under the constraint of test power. Finally, a BISR scheme allocation algorithm is proposed to allocate different BISR schemes for the RAMs under the constraints of the results of memory grouping and test scheduling. Simulation results show that the proposed MBiP can effectively plan the BISR schemes for the RAMs in a SoC. For example, about 22% area reduction can be achieved by the BISR schemes planned by the proposed MBiP framework for 50 RAMs under 1.5 mm distance constraint and 350 mW test power constraint in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit).

Built-in self-repair (BISR) techniques are widely used for repairing embedded random access memories (RAMs). One key component of a BISR module is the built-in redundancy-analysis (BIRA) design. This paper presents an effective BIRA scheme which executes the 2-D redundancy allocation based on a 1-D local bitmap. Two BIRA algorithms for supporting two different redundancy organizations are also proposed. Simulation results show that the proposed BIRA scheme can provide high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) for the RAMs with different fault distributions. Experimental results show that the hardware overhead of the BIRA design is only about 2.9% for an 8192 × 64-bit RAM with two spare rows and two spare columns. Also, the ratio of the BIRA analysis time to the test time is only about 0.02% if the March-CW test is performed. Furthermore, a simulation flow is proposed to determine the size of the 1-D local bitmap such that the BIRA algorithm can provide the best repair rate using the smallest-size 1-D local bitmap.

Three-dimensional (3D) integration using through silicon via (TSV) is an emerging technology for integrated circuit designs. 3D integration technology provides numerous opportunities to designers looking for more cost-effective system chip solutions. In addition to stacking homogeneous memory dies, 3D integration technology supports heterogeneous integration of memories, logic, sensors, etc. It eases the interconnect performance limitation, provides higher functionality, results in small form factor, etc. On the other hand, there are challenges that should be overcome before volume production of TSV-based 3D ICs becomes possible, e.g., technological challenges, yield and test challenges, thermal and power challenges, infrastructure challenges, etc.

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC'99 b19 benchmark is only about 0.15%.

Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core.

Modern processor and computation-intensive chips typically use the design style of multi-core chip architecture with identical logic and memory cores. Although memory built-in self-test (BIST) is a mature technique for testing embedded memories, testing multiple small memories using small area cost is still a challenge. This paper proposes a low area-cost BIST scheme for an array of memories and interconnections between memory cores and logic cores. To reduce the area cost without incurring long testing time, the BIST scheme tests multiple identical memories in a pipeline and each memory with a serial test interface. Experimental results show that the proposed BIST scheme has small area cost. For example, the proposed BIST scheme for 16 1024×64-bit RAMs only needs about 0.89% hardware overhead.

Built-in self-repair (BISR) techniques are widely used to enhance the yield of memories in a system-on-chip (SOC). A SOC typically consists of hundreds of memories. Cost-efficient BISR schemes for repairing those memories thus are imperative. In this paper, we propose a memory BISR automatic generation (MBAG) framework for designing memory BISR circuits in a SOC. The MBAG framework consists of a test scheduling engine and a memory grouping engine for the minimization of test time and area cost of the BISR circuits. The test scheduling algorithm has been presented in our previous work [1]. In this paper, therefore, we focus on the introduction of the grouping algorithm determining the memories which can share a BISR circuit under the constraints of distance and scheduling results. Simulation results show that the proposed MBAG can generate reconfigurable BISR circuits for 20 memories such that 50% area reduction is achieved in comparison with a dedicated BISR scheme if the distance constraint is 3mm and the test power constraint is 80mW.

This paper presents a march-like testTAC-Pto cover comparison faults of ternary content addressable memories (TCAMs) with asymmetric cells. The TAC-Ponly requires 4NWrite operations and (3N+2B) Compare operations for anN×B-bit TCAM with Hit and priority address encoder outputs. We show that the test also can cover search time failures induced by process variation in the comparison circuit of a TCAM. Furthermore, a test TMFfor match failures induced by the process variation in the comparison circuit of a TCAM is also presented.

Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded random access memories (RAMs). Fault-location ability of test algorithms executed by a BISR circuit has heavy impact on the repair efficiency of the BISR circuit. This paper proposes a defect-aware BISR (DABISR) scheme for single-port RAMs (SPRAMs) and multi-port RAMs (MPRAMs) in system chips. Multiple RAMs can share a DABISR such that the area cost of DABISR is drastically reduced. We also present two defect-location algorithms (DLAs) for identification of bridge defects between word-lines and bit-lines of MPRAMs. The DABISR can perform DLAs to locate bridge defects such that it can provide high repair efficiency. For example, simulation results show that if a faulty two-port RAM has 20% inter-port faults, the DLAs can help to gain 8.4-14.4% increase of repair rate for different redundancy configurations. In comparison with an existing shared BISR scheme, however, the DABISR only incurs about 0.34% additional area overhead to support the function of DLAs.

Ternary content addressable memory (TCAM) is one key component in high-performance networking applications. An asymmetric TCAM cell consists of a binary content addressable memory (BCAM) bit and a mask bit. In this paper, we analyze comparison faults of the asymmetric TCAM cell based on BCAM comparison faults. Also, two delay faults for covering delay defects in the comparison circuits of a TCAM are proposed. Then two march-like test algorithms THand TPAEare proposed to cover the comparison faults and delay faults of the comparison circuits in TCAMs with asymmetric cells. The test algorithm THrequires 7N Write operations and (3N + 2B) Compare operations to cover the comparison faults of an N × B-bit TCAM with Hit output only; and the test algorithm Tpae requires 4N Write operations and (3N + 2B) Compare operations to cover the comparison faults of an N × B-bit TCAM with priority address encoder (PAE) output.

This paper proposes a simple method for enhancing the reliability of static random access memories (SRAMs) with hard-to-detect resistive-open defects. The method prevents a SRAM from executing successive multiple read operations on the same position, such that the hard-to-detect defects cannot manifest as functional faults. This can prolong the lifetime of the SRAM with latent hard-to-detect defects. Experimental results show that the proposed reliability-enhancement circuit (REC) can effectively improve the reliability of the SRAMs without incurring delay penalty and with 0.07% additional area cost for an 8192 × 64-bit SRAM. By integrating the REC with the SRAM, a BISR scheme is proposed to boost 6%-10% increment of repair rate compared with the BISR without the REC. Also, the area cost of the BISR is low-only about 2% for an 8192 × 64-bit SRAM.

Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14 test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512 × 16 × 64-bit RAMs of which each RAM has one spare row and one spare column.

Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.

Embedded memory plays an important role in modern system-on-chip designs. However, the reliability issue of embedded memories becomes more and more critical with the shrinking of transistor feature size. This paper proposes a programmable online/off-line built-in self-test (BIST) scheme for random access memories (RAMs) with error correction code (ECC). The BIST scheme can be used for performing production testing and periodic transparent testing. In comparison with an existing transparent BIST scheme, the proposed BIST scheme does not incur the aliasing problem. Also, it can provide good fault location capability in online test mode. Experimental results show that the area cost of the proposed online/off-line BIST scheme is low-only about 2.6% for a 4Ktimes39-bit SRAM.

Ternary content addressable memory (TCAM) is a key component in various applications for its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fault models of TCAMs with asymmetric cells based on electrical defects. Some new comparison faults which do not exist in a TCAM with symmetric cells are found. A march-like test algorithm is also proposed to cover the defined comparison faults. The test algorithm consists of 8N Write operations and (3N + 2B) Compare operations for an N×B-bit TCAM with Hit output only.

Multicore system-on-chip (SOC) design is widely used for current high-performance applications. Multicore SOCs typically include a large amount of homogeneous memory cores (i.e., memory cores have the same size and configuration). This paper proposes a pipelined built-in self-test (PBIST) scheme for homogeneous memory cores in multicore SOCs. A PBIST circuit can be shared by clustered multiple homogeneous memories. This drastically reduces the hardware overhead of the PBIST circuit. A systematic procedure for converting a march test into a pipelined march test is also proposed. Experimental results show that the area overhead of a pipelined BIST for eight homogeneous 1k times 128-bit memories is only about 0.71%.

Embedded memories currently constitute a significant portion of the chip area for typical system-on-chip (SOC) designs. Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper proposes a shared parallel BISR scheme for random access memories (RAMs) in SOCs. The shared parallel BISR can test and repair multiple RAMs simultaneously. A global time-multiplexed built-in redundancy analyzer (TM-BIRA) is used to allocate redundancies of the RAMs under test and repair. We also design a 1500-compatible wrapper for chip-level control of the shared parallel BISR circuits. In comparison with the dedicated parallel BISR scheme (each memory has a self-contained BISR circuit), the proposed parallel BISR scheme can achieve 20% reduction of area cost by paying additional 0.005% test and repair time for serving 5 RAMs with spare rows and spare columns.

Ternary content addressable memory (TCAM) is one key component in the dedicated hardware modulars for high-performance networking applications. Symmetric and asymmetric cells are two widely used cell structures in TCAMs. An asymmetric cell consists of a binary content addressable memory (BCAM) bit and a mask bit. This paper proposes two march-like test algorithms, THitan TPAE, to cover the comparison faults of the BCAM cell and the comparison logic faults of the masking cell. Tan requires IN Write operations and (3N+2B) Compare operations to cover the comparison faults of an NtimesB-bit TCAM with Hit output only. TPAErequires 4N Write operations and (3N+2B) Compare operations to cover the comparison faults of an NtimesB-bit TCAM with priority address encoder (PAE) output.

Content addressable memories (CAMs) are widely used in digital systems. A test algorithm for CAMs must be able to cover the random access memory (RAM) faults and comparison faults. However, CAM circuits are usually customized for different products, so there are no standard tests, i.e., tests should be adapted to a specific design manufactured using specific technology. This paper presents a fault simulator, called CAM Evaluation tooL (CAMEL), for the evaluation of fault coverage of CAM test algorithms. It supports five common functional outputs, i.e., Data I/O, hit, multi-hit, matchout, and priority address for various CAM specifications. Since coupling fault simulation dominates the efficiency of a memory fault simulator, a concept of observability is proposed to simplify the coupling fault behavior. By exploiting the observability, a compression technique is also proposed to speed up the fault simulation and reduce memory usage. CAMEL can support both RAM faults and comparison faults. We have demonstrated the CAMEL using widely-used March tests and CAM tests. Simulation results show that the CAMEL can evaluate the fault coverage of tests accurately and efficiently.

Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 times 128-bit MPRAM with 1 spare row and 1 spare IO.

Ternary content addressable memory (TCAM) plays an important role in various applications for its fast lookup operation. This paper proposes several comparison fault models (i.e., the faults cause Compare operation fail) of TCAMs based on electrical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. TwoMarch-like tests for detecting comparison faults are also proposed. The first Marchlike test requires 4N Write operations, 3N Erase operations, and 4N + 2B Compare operations to cover 100% of targeted comparison faults for an N × B-bit TCAM with Hit output only. The second March-like test requires 2N Write operations, 2N Erase operations, and 4N + 2B Compare operations to cover 100% of targeted comparison faults for an N × B-bit TCAM with Hit and Priority Address Encoder outputs. Compared with the previous work, the proposed tests have lower time complexity for typical TCAMs; they can be used to test TCAMs with different comparator structures; and their time complexities are independent of the number of stuck-on faults. Also, they can cover delay faults in comparison circuits.

This paper presents a systematic procedure for transforming a bit-oriented March test into a transparent word-oriented March test. The test-time complexity of the transparent word-oriented March tests converted by the proposed method is only (P + 5 log2B + 2)N for an N x B-bit Random Access Memory, and the test-time complexity of the corresponding signature-prediction test is QN. Here, P and Q denote the number of total Read/Write and Read test operations of the original bit-oriented March test. A transparent-test methodology for memories with error-correction code (ECC) is also proposed. This methodology can test and locate faulty cells, and no signature prediction is needed. The test-time complexity of the proposed transparent-test methodology for memories with ECC is only (P + 5 log2B + 2) N.

Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair for one memory each time. In the repair mode, the proposed IIP can execute various redundancy analysis algorithms. Therefore, the user can select a better redundancy analysis algorithm for each memory core being tested according to its redundancy structure. Simulation results show that the proposed IIP needs less test time and redundancy analysis time than the processor-based built-in self-repair scheme. We also have realized the proposed IIP for four types of memories - two 8 K 64 bit SRAMs, one 4 K x 16 bit SRAM, and one 2 K x 32 bit SRAM - based on TSMC 0.18-mum standard cell technology. Simulation results show that the area overhead of the IIP is only about 4.6%.

With the nanometer-scale semiconductor technology, built-in self-repair (BISR) schemes are emerging techniques for improving the yield of embedded memories. A built-in self-repairable memory system typically consists of repairable memory cores, wrappers, built-in self-test (BIST) circuit, fuse group, and built-in redundancy-analyzer. This paper presents a system-level verification methodology for built-in self-repairable memory systems. The proposed verification methodology can verify the connectivity between the wrappers and self-repairable memories in a self-repairable memory system. Also, it can verify the wrapper misplaced design errors

Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-on-chips (SOCs). To increase the utilization of memory redundancy, the BISR technique usually needs to perform built-in redundancy-analysis (BIRA) algorithm for redundancy allocation. This paper presents an efficient BIRA scheme for embedded memory repair. The BIRA scheme executes the 2D redundancy allocation based on the ID local bitmap. This enables that the BIRA circuitry can be implemented with low area cost. Also, the BIRA algorithm can provide good repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the optimal scheme for the memories with different fault distributions. Also, the ratio of the analysis time to the test time is small.

With the shrinking feature size and the growing density, testing neighborhood pattern-sensitive faults (NPSFs) of integrated circuits is more and more important, especially testing NPSFs of semiconductor memories. This paper presents a test algorithm for detecting the active NPSFs (ANPSFs) in ternary content addressable memories (TCAMs). Due to the special TCAM cell structure, unique test algorithm with only march-based test operations or only two-group test operations is not efficient. We propose a test methodology with both march-based and two-group tests to cover 100% ANPSFs in TCAMs. The total test complexity is 156 for an -bit TCAM. Also, no TCAM circuit modification is needed to support the proposed test methodology.

This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple repairable RAM cores with different sizes and redundancy organizations (i.e., spare rows/spare columns or spare rows/spare IOs). We also propose an efficient built-in redundancy-analysis (BIRA) algorithm for allocating redundancies for the ReBISR scheme. A reconfigurable BIRA (ReBIRA) circuit is realized to perform the proposed BIRA algorithm for the ReBISR scheme. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). The area cost of the reconfigurable BIRA is very small, e.g., the area cost is only about 1.5% if 512times4times256 design parameters and four memory instances (64times2times32, 128times2times64, 256times4times128, and 512times4times256) are considered. Also, the ratio of the redundancy analysis time to the test time is very small, e.g., the ratio for a 512times4times256-bit memory tested by a March-14N algorithm with solid data backgrounds is only about 0.25%

With the increasing demand for high-performance networking application, network components such as network interfaces and routers are built in dedicated hardware modulars. Content addressable memories (CAMs) play an important role in the network components. Testing CAMs is very complicated due to their special structure. This paper presents an efficient March-like test algorithm for detecting the comparison faults of ternary CAMs based on the comparison fault models of binary CAMs. The test algorithm requires 5N Write operations, 2N Erase operations, and (3N + 2B) Compare operations for an N x B-bit TCAM.

Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has a heavy impact on the reliability of SOCs. The transparent test is a useful technique for improving the reliability of memories during their life time. The paper presents a systematic algorithm used for transforming a bit-oriented march test into a transparent word-oriented march test. The transformed transparent march test has shorter test complexity compared with those proposed previously (Nicolaidis, M., IEEE Trans. Computers, vol.45, no.10, p.1141-56, 1996; Thaller, K. and Steininger, A., IEEE Trans. Reliability, vol.52, no.4, p.413-22, 2003). For example, if a memory with 32-bit words is tested with March C-, the time complexity of the transparent word-oriented test transformed by the proposed scheme is only about 56% and 19% of the time complexity of the transparent word-oriented test converted by the schemes reported by Nicolaidis and by Thaller and Steininger, respectively.

Content addressable memory (CAM) is one key component in many digital systems. Although the CAM cell usually is implemented with RAM cell and comparison logic, the CAM testing is more difficult than the RAM testing. Also, the CAM testing is very different from the RAM testing. Most stuck-at faults (SAFs) in the RAM peripheral circuitry can be mapped to the RAM cell faults. This cannot be analogous to the testing of the priority encoder of CAMs. This paper presents a test algorithm for testing SAFs of the priority encoder in a CAM. The test algorithm only requires 3N - 2 Write operations and N + 2 compare operations to cover 100% stuck-at faults of the CMOS priority encoder of an N /spl times/ B-bit CAM. Compared with typical tests for CAM cell array faults, the fault coverage of SAFs in the priority encoder is increased from 90.2% or 60.5% to 100% for a CAM with 64 words.

This paper presents the comparison faults of TCAMs based on physical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Accordingly, several comparison fault models are proposed. A March-like test algorithm for comparison faults is also proposed. The test algorithm only requires 4N Write operations, 3N Erase operations, and (4N+2B) Compare operations to cover 100% comparison faults for an N /spl times/ B-bit TCAM. Compared with the previous work, the proposed test algorithm has lower time complexity for TCAMs with wide words and the time complexity is independent of the number of stuck-on faults. Also, the algorithm can cover all defects that cause a failed Compare operation. Moreover, it can be realized by built-in self-test circuitry with lower area cost.

This brief presents a built-in self-repair (BISR) scheme for semiconductor memories with two-dimensional (2-D) redundancy structures, i.e., spare rows and spare columns. The BISR design is composed of a built-in self-test module and a built-in redundancy analysis (BIRA) module. The BIRA module executes the proposed RA algorithm for RAM with a 2-D redundancy structure. The BIRA module also serves as the reconfiguration unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the BISR scheme. The BISR circuit has a low area overhead-about 4.6% for an 8 K /spl times/ 64 SRAM.

Diagnosis techniques are important for memory yield improvement. This paper presents an efficient diagnosis scheme for RAMs. The diagnosis scheme is composed of three March-based algorithms. A March-15N algorithm is used for locating and partially diagnosing faults of bit-oriented or word-oriented memories, where N represents the address number. Then a 3N March-like algorithm is used for locating the aggressor words (bits) of coupling faults in word-oriented (bit-oriented) memories. It also can distinguish the faults which cannot be identified by the March-15N algorithm. Thus the proposed diagnosis scheme can achieve full diagnosis and aggressor location with (15N + 3mN) read/write operations for a RAM with m CFs. Subsequently, an adaptive March-like algorithm is also proposed to locate the aggressor bit in the aggressor word with 4log/sub 2/B read/write operations, where B is the word width. Analysis results show that the proposed diagnosis scheme has higher diagnostic resolution and lower time complexity than other known fault location and fault diagnosis approaches.

This paper presents efficient testing methodologies for conditional sum adders. A conditional sum adder consists of conditional cells and selection cells. We propose a design-for-testability (DFT) technique to modify the conditional cells of a conditional sum adder. Then a test scheme is used for detecting the conditional sum adder with single cell fault model (CFM). The proposed test scheme only needs very low-test complexity to test a conditional sum adder. For example, the number of test patterns for a 64-bit conditional sum adder is only 9. The ratio of the number of test patterns of the proposed test scheme to the number of the test patterns of the previous scheme (Becker et al., 1995) is only about 1%. Also, experimental results show that the area overhead is only about 2.8% for a 64-bit conditional sum adder with the DFT scheme.

Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. Our BIST circuit supports three test modes: the 1) main memory testing, 2) spare memory testing, and 3) repair modes. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns. The BIRA module also serves as the reconfiguration (address remapping) unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the proposed RA algorithm and BISR scheme. The BISR circuit has a low area overhead—about 4.6 % for an 8K¢64 SRAM.

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.

System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design-for-testability methodologies are usually required for testing different cores. Another issue is test integration. The purpose of this paper is to present a hierarchical test scheme for SOC with heterogeneous core test anti lest access methods. A hierarchical test manager (HTM) is proposed to generate the control signals for these cores, taking into account the IEEE P1500 Standard proposal. A standard memory BIST interface is also presented, linking the HTM and the memory BIST circuit. It can control the BIST circuit with the serial or parallel test access mechanism. The hierarchical test control scheme has low area anti pin overhead, and high flexibility. An industrial case using this scheme has been designed, showing an area overhead of only about 0.63%.

Embedded content addressable memories (CAMs) are important components in many system chips. In this paper two efficient March-like test algorithms are proposed. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N+W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N/spl times/W-bit CAM. The second algorithm uses 3N log/sub 2/ W Write and 2W log/sub 2/ W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. Fault-location algorithms are also developed for locating the cells with comparison faults.

We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usually are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented. It guarantees 100% combinational fault coverage with negligible hardware overhead-about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones-a factor of up to 1/(6 /spl times/ 2/sup 5n/), where n is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By property exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented with no additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from O(N) to O(1). For both testing and diagnosis, the hardware overhead for our approach is only about 0.43% for 16-bit numbers regardless of the FFT network size.

In this paper we present a data compression technique that can be used to speed up the transmission of diagnosis data from the embedded RAM with built-in self-diagnosis (BISD) support. The proposed approach compresses the faulty-cell address and March syndrome to about 28% of the original size under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. The proposed compression technique reduces the time for diagnostic test, as well as the tester storage capacity requirement.

Diagnosis technique plays a key role during the rapid development of the semiconductor memories, for catching the design and manufacturing failures and improving the overall yield and quality. Investigation on efficient diagnosis algorithms is very important due to the expensive and complex fault/failure analysis process. We propose March-based RAM diagnosis algorithms which not only locate faulty cells but also identify their types. The diagnosis complexity is O(17N) and O((17+10B)N) for bit-oriented and word-oriented diagnosis algorithms, respectively, where N represents the address number and B is the data width. Using the proposed algorithms, stuck at faults, state coupling faults, idempotent coupling faults and inversion coupling faults can be distinguished. Furthermore, the coupled and coupling cells can be located in the memory array. Our word-oriented diagnosis algorithm can distinguish all of the inter-word and intra-word coupling faults, and locate the coupling cells of the intra-word inversion and idempotent coupling faults. With additional 2B-1 operations, the algorithm can further locate the intra-word state coupling faults. With improved diagnostic resolution and test time, the proposed algorithms facilitate the development and manufacturing of semiconductor memories.

Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.