This paper introduces the Functionality-Driven Multi-Agent Group Relative Policy Optimization (FD-MAGRPO) algorithm, which is designed to enhance exploration efficiency in reinforcement learning (RL) for analog integrated circuit sizing. Our proposed method integrates two key innovations: (1) a critic-free multi-agent optimization framework based on Group Relative Policy Optimization (GRPO), that eliminates the critic network and achieves stable and efficient policy updates; and (2) a functionality-driven grouping strategy, that enables agents to coordinate exploration by functional roles instead of circuit blocks, thereby improving credit assignment and cooperation. Experimental results on practical low-dropout regulator (LDO) circuits with 65–179 design parameters show that the proposed method achieves rapid convergence with only 800–3000 simulations, yielding a 4.8×–13.0× speedup over state-of-the-art methods. Mathematical analysis and empirical studies validate that the combination of critic-free optimization and functionality-based grouping leads to higher exploration efficiency and faster convergence. The proposed method enables the discovery of higher circuit performances that are inaccessible to conventional approaches, establishing FD-MAGRPO as a robust and efficient solution for complex analog-LDO sizing tasks.

This summary presents a 100 V output hybrid boost converter for an acoustic display driver. The proposed design incorporates two switched-capacitor topologies, the Fibonacci and Dickson topologies, to balance the on-chip area of power switches and the number of off-chip capacitors. The power stage utilizes laterally diffused N-type MOS (LDMOS) devices to enhance overall performance. A stacked active bootstrap circuit is employed to ensure sufficient gate driving voltage in multilevel bootstrapping, thereby preventing forward voltage drops from the passive diode. The converter achieves a voltage conversion ratio (VCR) of $20-40 \times$, with a maximum output voltage of 100 V from an input of $2.5-5 \mathrm{~V}$. It delivers a maximum output power of 2 W, peak efficiency of 86.2%, and a power density of $7.43 \mathrm{~W} / \mathrm{cm}^{3}$.

A hybrid sigma converter integrated with a digital low dropout (DLDO) regulator is presented in this paper and designed for high-density power delivery applications. The proposed converter employs an input-series and output-parallel (ISOP) topology, combining a high-side hybrid converter for high power efficiency and a low-side DLDO for rapid transient regulation. An auxiliary control loop minimizes the DLDO’s dropout voltage across wide input and output voltage ranges, eliminating efficiency degradation under non-optimal operating conditions. The converter achieves a peak efficiency of 92%, with a system power density of $101.3 \mathrm{~W} / \mathrm{cm}^{3}$. A $1.6 \mu$ s response time and $\mathbf{3 6 m V}$ voltage droop are achieved with a $\mathbf{2 A}$ load transient.

This paper presents a hybrid step-up converter with only one inductor and one flying capacitor. The proposed converter features a left-half-plane zero rather than a right-half-plane one. With a broad bandwidth up to a tenth of the switching frequency, the converter can attain a fast transient response as a buck converter. In addition, the voltage conversion ratio of the proposed converter is identical to that of the conventional boost converter, thereby enabling a wide range of output voltage in systems powered by lithium-ion batteries. Measurement results demonstrate that a peak efficiency of 95.1% is obtained. Given a load current stepping from 50 mA to 500 mA in less than 160 ns, the settling time is merely $2.8 \mu \mathrm{~s}$.

This paper presents a $\mathbf{2 M H z}$ relaxation oscillator (ROSC) designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (C-FIA) is adopted such that (1) the requirement of comparator speed is significantly alleviated and (2) the power consumption of the amplifier is further reduced. The proposed ROSC was fabricated in a 180 nm CMOS process and occupies only $0.1 \mathrm{~mm}^{2}$ active area. The measurement results with 8 samples show that the average power consumption is only $2.93 \mu \mathrm{~J} /$ cycle $(\mu \mathrm{W} / \mathrm{MHz})$ at 1 V supply voltage at room temperature. The average standard variation of the period jitter is 345 ps, which is as low as 0.068% of the 500 ns typical oscillation period (Tosc).

Analog circuit sizing remains a critical bottleneck in integrated circuit design, requiring extensive manual effort and computational resources. While multi-agent reinforcement learning (MARL) accelerates optimization through parallel agent training, existing approaches rely on manual circuit block clustering that fails to capture functional relationships between parameters. This paper presents ACEMARL, an adaptive clustering framework that automatically discovers functionally similar parameter clusters. ACEMARL integrates Bi-population Covariance Matrix Adaptation Evolution Strategy (BIPOP-CMA-ES), a high-performance evolutionary algorithm, for multi-modal exploration with data-driven clustering, aiming for automatic agent assignment. Experimental validation on amplifier and low-dropout regulators with up to 179 parameters demonstrated 3.3-5.0× faster convergence and 5.7-38.5% Figure-of-Merit (FoM) improvement compared to state-of-the-art (SOTA) block-based methods. The framework reduced confidence interval width by 31.6-60.7% along mean reward trajectories, enabling fully automated analog circuit sizing with improved stability and performance.

A fully-integrated reconfigurable switched-capacitor converter (SCC) that achieves very low voltage conversion ratios (1/4X, 1/5X and 1/6X) in a 65nm CMOS process is presented. It has three topological phases, and the SCC achieves minimum output resistance for every topology. An analysis is proposed to optimize the system efficiency with the consideration of charge redistribution loss, conduction loss, gate drive loss and bottomplate parasitic loss.

This paper presents a monolithic single-stage, 4-phase switched-capacitor (SC) hybrid boost converter with 11-to-$20\times $voltage conversion ratios (VCRs). The 4-phase operating SC hybrid topology is proposed to achieve high VCRs with only three flying capacitors and one inductor. With the SC topology, the average inductor current and the inductor current ripple are much reduced, releasing both power loss and size requirement for the inductor. A four-phase pulse width modulation (PWM) controller is proposed. A successive ramp generation scheme ensures identical pulse widths across three consecutive phases. A driver-assisted auxiliary charge pump provides sufficient driving voltages for the high-side driver and simplifies the overall circuitry. The proposed hybrid boost converter was implemented in a$0.18~\mu $m process. The measurement results show that the converter achieved a 20-24V output voltage range with a 1.2-1.8 V input voltage. 76.7% peak efficiency was achieved at$13\times $VCR and power density was 12 mW/mm3.

This paper presents a 2MHz relaxation oscillator designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (FIA) is adopted such that 1) the requirement of comparator speed is significantly alleviated and 2) the power consumption of the amplifier is further reduced. The proposed relaxation oscillator was fabricated in a 180nm CMOS process and occupies only 0.1mm2active area. The measurement results with 8 samples show that the average power consumption is 2.93μJ/cycle (μW/MHz) at 1V supply voltage at room temperature. The average standard variation of the period jitter is 345ps, which is 0.068% of 500ns typical oscillation period (TOSC). The measured temperature coefficient is 128ppm/∘C within the 0 to 90∘C range, and the voltage variation is 0.74%/0.1V from 0.95V to 1.15V. It scores a high phase noise figure-of-merit of 148dBc/Hz at 10kHz offset frequency.

This paper presents a high-precision bandgap voltage reference (BGR) using a low-cost current trimming network. The high-order curvature compensation is implemented by injecting a current with concave temperature curve characteristics into the bandgap core circuit. Meanwhile, a current-based trimming circuit is proposed to obtain a precise reference voltage while reducing the circuitry complexity and area consumption. Compared with traditional resistor-based trimming networks, the proposed trimming scheme does not require large-area resistors and complex digital logic circuits. Compared with prior current-based trimming scheme, the proposed one does not require extra current mirrors. The proposed BGR was designed in a 180nm BCD process and post-layout simulation results show that the temperature coefficient (TC) is lower than 2.3 ppm/°C within a wide temperature range of -40℃ to 125℃. Additionally, the power supply rejection ratio (PSRR) of -69dB at 100Hz is achieved. The active area of the proposed BGR is 383 µm × 259 µm, where the area of the proposed trimming circuit only occupies 16%.

This paper proposes a D2buck converter that achieves higher efficiency than the double-step-down (DSD) converter driving medium load current. It also minimizes undershoot and recovery time of load transient response. The D2buck converter consists of two buck converters in cascade, with the first handling high input voltage and low input current, and the second using low-voltage power switches to enhance efficiency. By implementing a sawtooth generator with well-defined thresholds, the undershoot detector realizes both delay-insensitive response and adaptive on-time extension during load transient. This work is designed in a 180nm BCD process. The first stage converts 24V to 4V, and the second stage converts 4V to 1V. For a load increase from 0.1A to 1.1A with an edge time of 20ns, the worst-case undershoot was better than 15%, and the recovery time was 2.7µs. The simulated peak efficiency was 91.9% with the load current ranging from 0.1A to 4A.

This paper presents a fully-integrated flexible dual-ring switched-capacitor (SC) converter to address the limited output voltage resolution in conventional SC converters. Based on the concept of reconfiguring multiple SC cells in series, the proposed dual-ring SC (DRSC) converter offers various combinations of cascading stages through the outer main ring configuration. Furthermore, the inner sub-ring operation allows for a more flexible selection of output nodes, enabling different power path interconnections and increasing the number of available voltage conversion ratios (VCRs). With 9 fractional VCRs, the converter offers a wide output range and fine output resolution. Compared to traditional SC topologies, the proposed topology exhibits the lowest slow switching limit resistance (R$_{\mathrm {SSL}}$) and the most favorable G-V2 metric, indicating high power efficiency. In addition, to reduce the parasitic capacitance, triple-well junction capacitors with increased reverse bias voltage were proposed. Parasitic capacitance with as low to 0.4% of the main capacitance was achieved. 3.9% efficiency improvement was measured. The chip was fabricated in a 180nm CMOS process and measured with 83% peak efficiency and 200mA maximum load current.

This paper presents a fully-integrated reconfigurable dual-ring switched-capacitor (DRSC) converter that overcomes the coarse output voltage resolution limitation of traditional switched-capacitor (SC) converters. The proposed DRSC converter cascades multiple stages of SC cells and achieves a fine voltage conversion ratio resolution from 1/n to (n-1)/n, where n is the number of phases. To improve efficiency, the bottom-plate parasitic loss is mitigated by the charge redistribution technique. Also, the power switches are divided into several segmentation groups to reduce the output ripple with different loads. This work is designed in a 180nm CMOS process with 30 cascaded reconfigurable SC power cells. It achieves a wide output voltage range of 0.5-3.3V from a battery input voltage (2.7-4.2V). The load regulation is implemented with a pulse-frequency modulation (PFM) control. The simulated peak efficiency is 78%, with a load current range of 0 to 20mA, using 1.5nF on-chip capacitors in total.

A half-bridge enhancement-mode GaN driver with closed-loop digital calibration is proposed to regulate the VGSringing to the desired device margin to optimize the slew-rate without compromising reliability. The highside and lowside have independent calibration loops for maximum flexibility, each with 8-bit resolution to cover a wide range of package inductance from 200 pH to 2 nH and GaN devices from as small as EPC2036 to as large as EPC2204. A limited bootstrap driver and a shoot-through guarded negative rail are also included to avoid overvoltage during deadtime periods and false turn-on during Miller plateau periods. This work is designed in a 180-nm BCD process and simulated to verify its functionality under different PVT corners and with different parasitic inductance and EPC GaN transistors. The envelop peak detector, which is the core component that determines the accuracy of ringing regulation, shows a maximum error of 6.2% over PVT corners up to 1 GHz of ringing frequency.

This paper proposes a piezoelectric energy harvesting interface circuit using multiple charge extractions and the multiple precharge (MCE-MPC) technique. This circuit is able to extract energy from PEH efficiently using a miniscule inductor and has the advantage of controllable precharge energy. It improves output power and extraction efficiency by using precharge and multiple transfers techniques. When the inductor value is 50μH, the output power of MCE-MPC is increased by 101.92% and 24.60% compared with synchronous electric charge extraction (SECE) and multi-shot SECE (MCE), respectively, and 7.62% compared with multiple charge extractions with bias-flip (MCEBF) when precharging the piezoelectric voltage to the same value. When the inductor value is 1mH, an extraction efficiency of 102.9% can be obtained by MCE-MPC.

A fully integrated single-input dual-output switched-capacitor converter with dynamic power-cell allocation for application processors is presented in this summary. The power cells can be dynamically allocated according to the loads, and the efficiency is improved by 4.8%. A dual-path voltage-control oscillator (VCO) that works independently of the power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross regulation.

A switched-capacitor DC-DC converter with a low output voltage ripple and high efficiency is presented in this summary. To achieve a wide input and output voltage range, a 3-clock-phase operation is proposed to achieve 6 voltage conversion ratios (VCRs) with only two discrete flying capacitors. A digital ripple reduction scheme is utilized to achieve up to four times reduction in output voltage ripple. The digital design also improves the design flexibility. The converter can deliver a 250mW maximum power to a wide output range of 0.5 V to 3 V with an input range of 1.6 V to 3.3 V, and achieves a peak efficiency of 91%.