The filtering-by-aliasing (FA) receivers have demonstrated sharp analog finite impulse response (FIR) filtering by combining periodically time-varying (PTV) circuit elements with uniform sampling. Seen at the sampled output, the impulse response of an FA receiver can be controlled by the PTV resistor’s resistance that varies over time, which realizes very sharp filtering with 50–70-dB stopband rejection. However, the finite stopband rejection and the inherent sampling in FA result in unwanted in-band residual blocker aliases, which cannot be suppressed further by downstream linear time-invariant (LTI) stages, unlike in a conventional receiver, and the overall blocker rejection may be insufficient in some applications. This paper describes a digital residual alias cancellation technique tailored for the FA receivers. By using a second channel to capture the blocker and equalizing the blocker in the FA and the second channels with digital baseband filters, measurement results, with the cancellation algorithm implemented in MATLAB, show that the residual blocker aliases can be suppressed by another ~15 dB, in addition to the FA analog filtering.

There has been a growing trend of developing programmable transceivers, which are the key to realizing a true software-defined radio [1]. Some prior works, such as N-path filters and mixer-first receivers, utilized periodically time-varying (PTV) circuits and have shown some promises and achieved what conventional time-invariant circuits are incapable of. Among them, the filtering-by-aliasing (FA) receivers [2], [3] have demonstrated good potential by showcasing sharp bandpass filters with good linearity and programmability.

Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost benefits. However, designing such a system has several challenges such as power delivery, clock distribution, waferscale-network design, design for testability and fault-tolerance. In this work, we discuss these challenges and the solutions we employed to design a 2048-chiplet, 14,336-core waferscale processor system.

A two-stage large-capacitive-load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain- bandwidth product (GBW). Implemented in a standard 0.13-μm CMOS technology and powered by a 0.7 V supply with a current consumption of 20 μA, the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a capacitive load of 9.5 nF. The average slew rate is 0.3679 V/μs. The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.

A gain and slew rate enhancement technique for amplifiers, based on starving current in static state and feeding excessive current during slewing, is proposed in this paper. Demonstrated in a current-mirror amplifier using a standard 0.18-μm CMOS process, the dc gain is boosted by 15 dB, and the slew rate is enhanced by over 600% compared with a conventional current mirror amplifier and 1100% compared with a current-starved amplifier. In the meanwhile, static power consumption is reduced by more than 2/3 without sacrificing unity-gain frequency, output swing or stability. The total power dissipation is only 63.4 μW under 1.8 V supply.