This paper reports an ultra-low voltage (ULV) relaxation oscillator (RxO) suitable for self-powered devices, designed with a pair of asymmetric swing-boosted (ASB) RC networks. This work enhances low-voltage operational capabilities and improves frequency stability and jitter performance. The RxO features a unique single amplifier configuration incorporated with a customized feedback mechanism that effectively compares the output voltages from the RC networks, substantially reducing jitter due to flicker noise. Additionally, we implement a Duty-Cycling Circuit (DCC) based on a DLL architecture to turn on the amplifier before the desired detection point, providing ample guard time and thereby reducing power consumption, which is essential for ultra-low power applications. The RxO also features a Replica Temperature Compensation Circuit (RTCC) to mitigate circuit delay. Fabricated in 65-nm CMOS, the RxO operates at 2.35 MHz with a minimal supply voltage of 0.5 V, achieving a period jitter of 390 ppm and line sensitivity of 17.4%, and an energy efficiency of 5.82 pJ/cycle. The device demonstrates significant improvements over existing ULV designs, achieving up to 60% reduction in power consumption while maintaining lower jitter levels.

This article presents a 24-MHz fast startup crystal oscillator (XO) with a phase-interpolator-assisted synchronized injection technique. The technique ensures phase consistency between the injection source and the crystal resonance, even with a 2% injection-$\Delta F$, enhancing the robustness of the startup under different PVT conditions. Additionally, we propose a differential peak detection technique to detect the phase error incurred by$\Delta F$. Such a peak detection technique shortens the auxiliary non-injection period during startup to merely four cycles, thereby maximizing the injection percentage to 97.4% and enhancing the startup’s efficacy. Fabricated in the 40-nm CMOS process, the XO achieves a 6.9-$\mu $s startup time (166 cycles) with a startup energy of 4.8 nJ under a 1-V$V_{\text {DD}}$. Furthermore, the startup time varies by ±4.4%, ±3.6%, and ±5.1% (worst case) over$\Delta F$(0.25% to 2%), temperature (−40 to$85~^{\circ }$C), and$V_{DD}$(0.95 to 1.05 V) variations, respectively. The XO’s phase noise in the steady-state is −137.8dBc/Hz at the 1-kHz offset, with a power consumption of$63~\mu $W.

This work proposes a single-point linear-regression-assisted trimming method for a MOSFET-based voltage reference to reduce operation verification complexity. By obtaining the correlation between the input features at a unique temperature and the output voltages across the operating temperature range from layout-aware Monte-Carlo simulations, we can build the linear regression model to predict the profile of the voltages across the temperature range based on eight input features. Hence, we can apply the appropriate trimming code on the circuits, avoiding time-consuming temperature characterization. We design the voltage reference in 65nm CMOS and obtained 8,000 sets of simulation data to train the regression model. Validated through simulation, we reduce the temperature coefficient of the voltage reference to 64.7ppm/°C using the proposed scheme, 26% lower than that of the conventional 2-point trimming, evincing the efficiency and accuracy of the linear-regression-assisted trimming.

Low-Power fully-integrated oscillators are the cornerstone of Internet-Of-Things devices due to their compactness, high energy-efficiency, and scalability. This paper presents a relaxation oscillator featuring double capacitor-charging headroom by applying chopping on the capacitor. Such an increase in the charging headroom soothes the frequency instability attributable to the comparator and logic gate’s delay, culminating in a more stable frequency output amid voltage and temperature variations. We designed and fabricated two 0.4V relaxation oscillators (803kHz and 428kHz) in the TSMC 65nm process. The measured temperature coefficients are 164 and 106 ppm/°C (averaged from 10 samples) across −20 to 120°C for the 803kHz and 428kHz relaxation oscillators, and the line sensitivities are 15.8%/V and 14.4%/V across 0.35 to 0.5V. Such results are improved by >1.8× and >11× compared with the reference oscillator with regular charging headroom. The oscillators’ long-term stabilities are 150 and 110 ppm with a 0.1s gating interval.

This paper presents a miniature magnetic resonance imaging (MRI) platform specifically designed for imaging small-volume samples (~1μL), making it particularly suitable for real-time and on-site biochemical sample monitoring. This innovative system employs an MRI application-specific integrated circuit (ASIC) for excitation and detecting the nuclear magnetic resonance (NMR) signal. To cope with the small-volume sensing, the platform features a customized frontend probe, which includes a miniaturized saddle coil and a PDMS-molded sample well to contain the microlitre-volume sample under observation. Our proof-of-concept measurements on small-volume samples demonstrate an MRI image resolution of 150 × 150 × 250μm3. These results highlight the system’s applicability and potential for future biological analysis, offering a promising tool for researchers in the field.

Being an indispensable technique in the standard laboratory, Nuclear Magnetic Resonance (NMR) is a versatile method to non-invasively observe the atomic and molecular information of the samples containing non-zero spin nuclei. Yet, the bulky and costly hardware for NMR impedes their broad distributions outside the laboratory for on-demand and on-line usage. In recent years, with the advance in microelectronics, NMR systems equipped with customized silicon chips emerged to achieve system miniaturization with performance enhancement, and pioneer novel applications that were not feasible before using discrete NMR electronics. This article overviews the hardware for NMR from the system-level perspective, and examines the latest developments using integrated circuits over the past decade. Also, we present in detail the design considerations of the transmitter and receiver that are the cornerstone of micro-NMR systems.

Wearable and sensing electronics are evolving towards energy harvesting from the environment (e.g. thermal and solar energy). Ultra-low-voltage (ULV) circuits that allow direct-powering by sub-0.5 V energy sources can maximize the power efficiency. This work is a 0.4 V 65 nm CMOS relaxation oscillator with bootstrapped logic gates and outputs. The bootstrapped logic gates enable an output swing of 1.15 V surmounting the adverse effect of ULV digital circuits without extra voltage source. The ULV comparator with bulk-driven-inputs shows an 18 dB gain with 3 cascaded stages. Also, featuring a background delay-time cancellation scheme, the 3.3 MHz relaxation oscillator with built-in calibration exhibits a frequency deviation of ±0.71% and ±0.57% against temperature (-30 to 100 °C) and voltage (0.36 to 0.44 V) variations, respectively, from Monte-Carlo simulations (N=30). The simulated power consumption is 6.4 μW, resulting in an energy efficiency of 1.9 pJ per cycle.

For ultra-low-power radios, the long startup time of the crystal oscillator dominates their on-off latency and limits their power efficiency. This paper describes the design of a 65nm CMOS 16MHz crystal oscillator, featuring a momentary detuning scheme to accelerate the startup transient. Specifically, during the startup phase, the bias current (266μA) and loading capacitors (8.5pF each) are enlarged concurrently such that the equivalent negative resistance of the oscillation loop can be momentarily enhanced, resulting in 74-fold reduction of the startup time (37ms → 0.5ms), while consuming just 53.2nJ at 0.4V. Also, a time-based controller automatically drives the oscillator into the steady state, which entails a smaller bias current (12μA) to sustain the oscillation, and smaller loading capacitors (5pF) to recover the proper oscillating frequency. The simulated phase noise exhibits -128.2dBc/Hz at 1kHz offset, resulting in a FoM of 265.5dBc/Hz.