Demo Data from EDBT 2026 / reviewers in the wild / expert
Anadi Mishra
dblp:159/0635
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Processor architecture and microarchitecture · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware/software co-design
custom instruction identification |
0.2 | 1 | 2015 | Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Electronic design automation
high-level synthesis |
0.2 | 1 | 2015 | Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Processor architecture and microarchitecture › instruction set architecture
instruction set extension |
0.1 | 1 | 2015 | Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Methods — techniques the papers use, named apart from their topics
graph enumeration · 0.2convexity analysis · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom InstructionsabstractAutomatic identification of custom instructions (CI) is the process of supporting the programmer in choosing automatically beneficial parts of the application source code that can then be synthesized and run on dedicated hardware. Identification is typically modeled as choosing a subgraph from a graph, representing the application, that has the highest speedup potential when implemented in custom hardware, and that fulfills the constraints of convexity and of a given maximum number of inputs and outputs. Existing algorithms for CI identification either enumerate all the valid subgraphs under the constraints of convexity and I/O, or return the subset of all maximal valid subgraphs with respect to convexity only. The downside of the former approach is that enumerating all valid subgraphs is costly, especially for large values of input and output constraints, while we may be interested in the subgraphs which obtain the best speedup only. Instead, the latter approach may fail to find a feasible solution, since the valid subgraphs with respect to convexity only can be too large to be useful. In this paper, we present a novel approach which attempts to fill the gap between the existing methods. In particular, we present an algorithm that enumerates the subset of all maximum valid subgraphs with respect to convexity and number of inputs and outputs. Our method revisits and combines the existing approaches and yields an algorithm which is effective and outperforms the state-of-the-art for large values of input and output constraints. Emanuele Giaquinta, Anadi Mishra, Laura Pozzi 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |