Digital scan-based automatic test pattern generation (ATPG) was recently described for ‘random analog’ circuits with >95% likelihood-weighted coverage of the shorts and opens prescribed by IEEE P2427, with test times99% coverage in <20 µs is possible for DACs that have a binary R-2R and/or unary segment resistor structure, and possibly other structures, with simple design-for-scan-test circuit changes that do not significantly affect performance or area. These DAC types are used in many applications because of their simplicity, speed, and area.

Scaling down the transistor size enables a cost-effective high-performing solution in modern semiconductor designs. However, the added complexity of process and extremely small critical three-dimensional spacing of the transistor structure make it more challenging to maintain precise variation control. Defects introduced here can lead to different intermittent behaviors, some of which might not appear as fails during traditional testing procedures but might manifest as a system failure in the field. The emergence of artificial intelligence chip design has introduced high demands for a massive number of multi-cores connected in parallel with a huge memory array size in a chip. This further increases the importance of identifying rare tail events through in-depth diagnosis in advanced nodes. Various sophisticated algorithms have been proposed to improve defect coverage. However, the addition of algorithms may increase test cost tremendously while providing limited benefits for specific fault types which may not happen. Therefore, selecting a smart combination of algorithms that provide enough coverage for the specific product application is essential for cost-effective testing. In this paper, we review the electrical properties of marginal defects inserted in an SRAM device to evaluate test escapes in the latest technology. We also present a new algorithm to improve test coverage efficiency. A commercially available memory BIST tool was used to load a DFT compatible algorithm and operation set for memory test. A commercially available analog simulation tool was used in combination with a novel defect simulation flow to evaluate digital and analog behavior of the device.

Scan-based automatic test pattern generation (ATPG) is commonly used for ‘random logic’ in ICs, but there is no equivalent for analog/mixed-signal (AMS) circuits due to their diversity of functions, stimuli, and responses. As a result, tests are written manually on the intended automatic test equipment (ATE) with (possibly defective) ‘first silicon’ devices, typically requiring months of effort and test times higher than for the digital circuitry. Proving the defect coverage of these tests in simulation is typically impractical, andth-order filter, bandgap + voltage regulator, 8-bit DAC, and industrial 11-bit SAR ADC achieve comparable or higher coverage of IEEE P2427-specified shorts and opens, relative to specification tests, in <1 ms. Defect coverage can be simulated in <1 hour, fast enough to verify before tape-out.

Recent papers have proposed methods for more efficient mixed-signal test generation, measuring test stimulus quality, and defect simulation. This paper addresses the most time-consuming remaining step to achieving higher quality mixed-signal ICs: diagnosing defects reported as undetected by an analog fault simulator. A unique method for automatically reporting the observability of each undetected defect is described that works for analog, mixed-signal, and even digital circuits (that don't have scan path access). Results are reported for an 8-bit SAR ADC from the ITC'17 A/MS benchmark circuits, and they reveal that most of the undetected defects can be quickly categorized into those that need a better test stimulus, those that need better output analysis, and those that might need better DFT.

The percentage of circuit elements stimulated by a test stimulus applied to a mixed-signal circuit is analogous to the toggle coverage of a test pattern applied to a digital circuit and can serve as an estimate of the quality of, or maximum test coverage achievable with, that stimulus. This paper proposes a novel definition for analog activity coverage and how to measure it in a defect-free circuit for any potential defects (shorts, opens, and parametric). Results are provided for the ITC'17 analog benchmark circuits and show that activity coverage is an approximate upper limit for defect coverage. Other uses for measuring test stimulus quality are discussed, such as assessing burn-in and over-voltage stress stimuli, and ensuring defect tolerance measured for ISO 26262 is accurate.

Analog simulation is much less efficient than digital simulation, so it is essential to reduce the number of potential defects to be simulated when assessing defect coverage of an analog circuit's test. Simple random sampling (SRS) is a published technique for digital fault sampling; stratified sampling is an improvement explored for analog fault simulation. This paper compares the defect coverage estimation accuracy of several sampling techniques and our improvements based on defect-likelihood-weighted selection, as measured by confidence interval. For practical cases, it is shown that the estimation accuracy of SRS gets progressively worse as defects become less uniform in likelihood, but with weighted selection, accuracy improves. We conclude that defect coverage can always be estimated sufficiently accurately by simulating fewer than a thousand defects (and usually much fewer), regardless of circuit size, analog/digital content, and defect likelihood distribution.