For the wearable biomedical signal detection, both high accuracy and low-power consumption are critical requirements. Various works have employed the neural network to improve the detecting accuracy and develop the biomedical processor. However, the biomedical processor with neural network engine contains massive data movements and large data buffers. One solution is the computing-in memory (CIM) architecture, which locates more data near the computing engine to reduce data movements. In traditional CIM-based solution, the detecting accuracy and power consumption is difficult to be optimized simultaneously, where the accuracy should be satisfied for the detection. To date, the time-domain computing engine have been developed to employ both digital and time domain computation. In this work, we present a high-precision time-domain engine to perform 8-bit multiplication and addition operation for the biomedical signal detection. With the high precision time-domain engine, we develop a CIM-based neural-network processor, namely TDPRO, to perform the detection of arrhythmia. In addition, we develop TD-zero-jumping (TDJ) and idle-shutdown (ISD) techniques according to signal features and data mapping strategy, further optimizing the power consumption. Based on our evaluation, the TD-based 8-bit mulitply-accumulation operation is robust, without declining the accuracy of biomedical signal detection. We design a ECG processor with the proposed TDPRO architecture, which obtains 98.60% high accuracy and 75.7% power saving compared to the recent the state-of-the-art study.

Recently wearable EEG monitoring devices with seizure detection processor using convolutional neural network (CNN) have been proposed to detect the seizure onset of patients in real time for alert or stimulation purpose. High energy efficiency and accuracy are required for the seizure detection processor due to the tight energy constraint of wearable devices. However, the use of CNN and multi-channel processing nature of seizure detection result in significant energy consumption. In this work, an energy-efficient seizure detection processor is proposed, featuring multi-stage CNN classification, segmented data processing and adaptive channel selection to reduce the energy consumption while achieving high accuracy. The design has been fabricated and tested using a 55nm process technology. Compared with several state-of-the-art designs, the proposed design achieves the lowest energy per classification (0.32 μJ) with high sensitivity (97.78%) and low false positive rate per hour (0.5).

In wearable biomedical signal detection, the low-power consumption is a critical requirement. However, the process of biomedical signal detection with traditional neural-network processor is uneconomical for large data movements. A typical solution is the near memory computing (NMC) method, locating more data near the computing engine to save energy, where the detecting accuracy and power consumption is difficult to be optimized simultaneously. In addition, a suitable computing engine is needed to match both power and computation budget. In this work, we combine the NMC-based ECG processor equipped with a high-precision time-domain engine to perform the detection of arrhythmia, namely TDPRO. The proposed TDPRO supports high precision multiplication and addition operation with 8-bit input and weight parameters. Also, we propose TD-zero-jumping and idle-shutdown technique to further reduce 63%$\sim$ 91% power consumption of the time-domain engine. The error rate of 8-bit MAC operation in the TDPRO is 1.18%, which is suitable for the ECG detection.

Emerging energy-efficient neural network processor is a promising hardware design to accelerate neural network algorithms with high performance and low power consumption. Typically, static random-access memory (SRAM) is employed to develop large buffers using in the processor. The bit cell of SRAM contains six transistors, leading to low density and large leakage current. In particular, several AI processors need multiple port and transfer-based SRAMs, which decrease the density and increase the power consumption. Recently, emerging spin-orbit torque magnetic random-access memory (SOT-MRAM) becomes a possible solution to replace the SRAM as working memory. However, more operations should be supported by the SOT- MRAM to provide sufficient functions, such as multiple-port memory, transpose memory, data-streaming operations. In this paper, we develop the working memory of neural network processor with SOT-MRAM to build the design library including the transpose operations, multiple-port memory, and data-streaming based buffer arrays. Equiped with those operations provided by SOT-MRAM, we can build high performance and energy-efficient neural network processors.