Implementing embedded neural network processing at the edge requires efficient hardware acceleration that combines high computational throughput with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly being adapted to support the improved functionalities. Hardware designers can refer to a myriad of accelerator implementations in the literature to evaluate and compare hardware design choices. However, the sheer number of publications and their diverse optimization directions hinder an effective assessment. Existing surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effects of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. In contrast to previous surveys, this work provides a quantitative overview of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. The list of optimizations and their quantitative effects are presented as a construction kit, allowing to assess the design choices for each building block individually. Reported optimizations range from up to 10,000× memory savings to 33× energy reductions, providing chip designers with an overview of design choices for implementing efficient low power neural network accelerators.

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as two transistors and that can be fabricated without additional process steps. However, since the performance of GC-eDRAMs relies on many interdependent variables, the optimization of the performance of these memories for the integration into their hosting system, as well as the design investigation of future GC-eDRAMs, prove to be highly complex tasks. In this context, modeling tools of memories are key enablers for the exploration of this large design space in a short amount of time. In this paper, we present GEMTOO, the first modeling tool that estimates timing, memory availability, bandwidth, and area of GC-eDRAMs. The tool considers parameters related to technology, circuits, and memory architecture and it enables the evaluation of architectural transformations as well as of advanced transistor-level effects, such as the increase of the access delay due to deterioration of the stored data. The timing is estimated with a maximum deviation of 15% from post-layout simulations in a 28nm FD-SOI technology for different memory sizes and architectures. Moreover, the measured random cycle frequency of a GC-eDRAM fabricated in 28nm CMOS bulk process is estimated with a 9% deviation when considering 6-sigma random process variations of the bitcells. The proposed GEMTOO modeling tool is used to show the intricacies in design optimization of GC-eDRAMs and, based on the results, optimal design practices are derived.

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. This problem is aggravated due to the impact of Process-Voltage-Temperature (PVT) variations at deeply-scaled technology nodes and low voltages. In this paper, we present a GC-eDRAM with body-bias compensated readout, which is dynamically configured to extend the data retention time (DRT) of the memory under varying operating conditions. The proposed GC-eDRAM exploits the body-biasing capabilities of FD-SOI technology to adjust the switching threshold of the sense inverter under PVT variations. An additional, unbiased, sense inverter is added to provide a dual-sampling mechanism to the readout path, enabling error detection to further reduce design guard bands. An 8 kb GC-eDRAM with integrated body-bias compensated readout and error detection was implemented in 28 nm FD-SOI technology. Silicon measurements of the manufactured array demonstrate up-to 75% DRT improvement and up-to 86% energy savings under PVT and frequency variations compared to a conventional guard banded memory design.

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as it relies on a storage cell that can be implemented with as few as two transistors and that can be fabricated without additional process steps. However, since the performance of GC-eDRAMs relies on many interdependent variables, the optimization of the performance of these memories for the integration into their hosting system, as well as the design investigation of future GC-eDRAMs, proves to be highly complex tasks. In this context, modeling tools of memories are key enablers for the exploration of this large design space in a short amount of time. In this article, we present GC-eDRAM modeling tool (GEMTOO), the first modeling tool that estimates timing, memory availability, bandwidth, and area of GC-eDRAMs. The tool considers parameters related to technology, circuits, and memory architecture, and it enables the evaluation of architectural transformations as well as advanced transistor-level effects, such as the increase in the access delay due to the deterioration of the stored data. The timing is estimated with a maximum deviation of 15% from postlayout simulations in a 28-nm FD-SOI technology for different memory sizes and architectures. Moreover, the measured random cycle frequency of a GC-eDRAM fabricated in a 28-nm CMOS bulk process is estimated with a 9% deviation when considering 6-sigma random process variations of the bitcells. The proposed GEMTOO modeling tool is used to show the intricacies in design optimization of GC-eDRAMs, and based on the results, optimal design practices are derived.

Embedded DRAM (eDRAM) requires frequent power-hungry refresh according to the worst-case retention time across PVT variations to avoid data loss. Abandoning the error-free paradigm, by choosing sub-critical refresh rates that gracefully degrade the eDRAM content, unlocks considerable power-saving opportunities, but requires to understand the effect of stochastic memory errors at the system/application level. We propose an FPGA-based platform featuring faulty eDRAM emulation based on advanced retention time models and silicon measurements for statistical error resilience evaluation of applications in a complete embedded system. We analyze the statistical QoS for various benchmarks under different sub-critical refresh rates and retention time distributions.

The rise of data-intensive applications has increased the demand for high-density and low-power embedded memories. Among them, the gain-cell embedded DRAM (GC-eDRAM) is a suitable alternative to the static random access memory (SRAM) due to its high memory density and low leakage current. However, as the GC-eDRAM dynamically stores data, its memory content has to be periodically refreshed according to the data retention time (DRT). Even though different DRT characterization methodologies have been reported in the literature, a practical and accurate method to quantify the DRT across Monte Carlo (MC) runs to evaluate the impact of local process variations (LPVs) has not been proposed yet. Thus, the minimum memory refresh rate is generally estimated with large design guard bands to avoid any loss of data, at the expense of a higher power consumption and less memory bandwidth. In this work, we present a current-based DRT characterization methodology that enables an accurate LPV analysis without the need of a large number of costly electronic design automation (EDA) software licenses. The presented approach is compared with other DRT characterization methodologies for both accuracy as well as practical aspects. Furthermore, the DRT of a 3-transistor (3T) gain cell (GC) designed in 28 nm FD-SOI process technology is measured for different design choices, global and local variations. The analysis of the results shows that LPVs have the most degrading effect on the DRT and therefore that the proposed approach is key for either the design of GC-eDRAMs or the choice of their refresh rate to avoid the need for overly pessimistic worst-case margins.

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate digital designs with such carefully controlled far-below-worst-case margins, ensuring their correct operation even in the presence of uncertainties and variations. However, these registers are often designed only to either detect setup timing violations or to measure the available positive timing slack for a small detection-window. In this paper we propose a timing-monitoring sequential that provides both timing-monitoring modes, which can be selected at run-time depending on the desired timing-monitoring strategy. As the detection window of the presented circuit depends on the duty-cycle of the clock, either slow paths or fast paths can be monitored and measured with wide timing windows. The performance of this timing-monitoring sequential is evaluated in a 28 nm FD-SOI process with post-layout simulations which show that the circuit is able to monitor a positive timing slack as small as 140 ps or to measure a path delay as fast as 50 ps. The proposed circuit is applied to a digital multiplier that was fabricated in a test chip and measurements show that the timing-monitoring sequentials are able to measure the critical path of the multiplier with a 1% accuracy and without incurring any timing violation.

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered (DET) clocking, as sequential elements operate at half the clock frequency while maintaining the same throughput as with conventional single-edge-triggered (SET) clocking. However, the DET approach is rarely taken in modern integrated circuits, primarily due to the perceived complexity of integrating such a clocking scheme. In this article, we first identify the most promising conditions for achieving low-power operation with DET clocking and then introduce a fully automated design flow for applying DET to a conventional SET design. The proposed design flow is demonstrated on three benchmark circuits in a 40nm CMOS technology, providing as much as a 50% reduction in clock distribution and register power consumption.

Dual-edge-triggered (DET) synchronous operation is a very attractive option for low-power, high-performance designs. Compared to conventional single-edge synchronous systems, DET operation is capable of providing the same throughput at half the clock frequency. This can lead to significant power savings on the clock network that is often one of the major contributors to total system power. However, in order to implement DET operation, special registers need to be introduced that sample data on both clock-edges. These registers are more complex than their single-edge counterparts, and often suffer from a certain amount of clock-overlap between the main clock and the internally generated inverted clock. This overlap can cause contention inside the cell and lead to logic failures, especially when operating at scaled power supplies and under process variations that characterize nanometer technologies. This paper presents a novel, static DET flip-flop (DET-FF) with a true-single-phase clock that completely avoids clock overlap hazards by eliminating the need for an inverted clock edge for functionality. The proposed DET FF was implemented in a standard 40nm CMOS technology, showing full functionality at low-voltage operating points, where conventional DET-FFs fail. Under a near-threshold, 500mV supply voltage, the proposed cell also provides a 35% lower CK-to-Q delay and the lowest power-delay-product compared to all considered DET-FF implementations.

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).