Neuromorphic computing is becoming common in diverse systems, including time-sensitive, real-time systems. This requires that large data sets be processed quickly with low latency. A stream processing architecture helps achieve this goal by beginning processing as soon as samples are received. In this paper, to achieve a low-latency implementation, neurons are parsed into fine-grain operations and scheduled onto stages of the pipeline. Wide datapaths that process multiple samples in each stage of the pipeline greatly improve throughput and latency. Also, the sparsity of partially connected neural networks allows proposed schedulers to further decrease latency. These schedulers use 'greedy' heuristics based on data dependencies to develop a reduced latency schedule. The schedulers were testing against sets of 1000 partially-connected neural networks, with sets ranging in number of layers from three to fifteen. The set of heuristics developed showed reductions of up to 67% over a sequential schedule.

Processing of parallel data streams requires permutation units for many algorithms where the streams are not independent. Such algorithms include transforms, multi-rate signal processing, and Viterbi decoding. The absolute order of data elements from the permutation is not important, only that data elements are located correctly for the next processing step. This paper describes a method to find permutations that require a minimum amount of memory and latency. The required permutations are generated based on the data dependencies of a computation set. Additional constraints are imposed so that the parallel streaming architecture processes the data without flow control. Results show agreement with brute force methods, which become computationally infeasible for large permutation sets.

Streaming architectures are a popular choice for data intensive application due to their high throughput requirements. When assembling components for a streaming application, it is often necessary to build translation blocks between them to match the ordering of the data elements required for the subsequent processing. This paper addresses this need by developing a technique that realizes arbitrary permutations in a streaming architecture. It is parametrized to accommodate any size data sequence and streaming width. This technique is applied to an architecture that receives continuous input at a rate of k elements per clock cycle, and after an initial start-up latency, outputs continuously at the same rate. In addition, the memory usage and latency through the memory array is minimized. This design is evaluated for permutations parametrized by size and stream width in terms of the memory elements and depths required. The class of stride permutation is considered for specific experimental evaluation. On average, this technique and architecture has only half the latency and requires half the memory of other techniques.