This paper proposes a 1.5 GS/s 9-bit two-stage pipelined SAR analog-to-digital converter (ADC) in 28 nm CMOS. Simultaneously with amplification, the inter-stage residue is converted to time-domain (TD) and quantized by a TDC. This results in significant resolution improvement of the second stage under the speed of 1.5 GS/s. A double-edge quantized TDC with improved time resolution is proposed for higher conversion speed in the time domain and less power consumption. Moreover, a cascode switching inverter-based open-loop amplifier is proposed featuring low gain error, fast settling, and low power. With a sampling speed of 1.5 GS/s, the simulation results show that the ADC achieves 55 dB SNDR and 66.7 dB SFDR at the Nyquist frequency and 1-Vppinput swing, while the power consumption is 6.86 mW, yielding a Walden FoM of 10.2 fJ/con-step.

This article presents a single-channel 4-GS/s 8-bit hybrid-domain analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. The proposed 8-bit ADC combines a 3-bit voltage-domain stage with a 6-bit time-domain (TD) backend to take full advantage of the voltage and time domains. A high-speed hybrid-loop residue amplifier (RA) is proposed with a settling time of less than 150 ps, while a non-symmetrical pipeline timing utilizing a 25% duty cycle clock is used to increase the TD quantization time and the settling time margin of the RA. A low-power and small-area gated-ring-oscillator-based TD backend is employed, which operates at 4-GS/s with 6-bit resolution. The prototype hybrid ADC occupies an active area of 0.0114 mm2. Under a 1-V power supply and Nyquist input, the chip achieves a measured ENOB of 6.46 bits at a conversion rate of 4 GS/s, while the power consumption is 10.6 mW and the FoMw is 29.9 fJ/conversion-step.

This article introduces a pulsed laser direct time-of-flight (dTOF) flash light detection and ranging (LiDAR) sensor fabricated in 0.18-$\mu \text{m}$HV CMOS technology. The chip includes$32\times 32$macro pixels and 1024 time-to-digital converters (TDCs). A noise filtering circuit with different threshold ($\text{N}_{\mathrm {th}}$) configuration is adopted in each macro pixel [formed by four single-photon avalanche diodes (SPADs)], which can suppress strong background light (BG) induced pile-up. To verify the imaging function and effectiveness of the noise filtering circuit, two systems are implemented (System1 for indoor imaging measurement and System2 for outdoor distance measurement). With the help of the noise filtering circuit and a reasonable signal-to-background noise ratio (SBR), the maximum detection range outdoors with reasonable accuracy can be greatly extended (from 12m @ Nth= 1 of System2 to more than 20m @ Nth= 2 of System2 under 70klux of background noise). The counter in the noise filtering circuit can be reused to get intensity information. A robust 13-bit TDC with a reliable reset is introduced. Thanks to a dedicated START/STOP logic and a Schmitt trigger, large TDC quantization errors can be avoided. It achieves a 200ps resolution (LSB) and exhibits an INLp-pof 3.55LSB and a DNLp-pof 0.53LSB. The maximum inter-frame rate can reach 270kfps with 16 IOs operating at speed of 500MHz. Combining 9k inter-frames to get one frame, a frame rate of 30 is achieved for an indoor 3-D imaging. For outdoor measurement, more laser pulses should be accumulated.

This article presents a 16-channel analog silicon photomultiplier (SiPM) with on-chip front-end for direct time-of-flight (D-ToF) LiDAR applications. The proposed receiver is mainly composed of 16-channel SiPM, variable gain amplifier (VGA) and time-to-digital converter (TDC). Each SiPM channel consists of 256 microcells, and their outputs are connected to a common output terminal in parallel. A novel active quenching circuit is adopted to reduce the long exponential tail in conventional SiPM and enable the capability of multi-echo detection. Current steering circuits are adopted within microcells to make the output current of SiPM immune to SPAD gain variations. The receiver was fabricated in 180-nm HV CMOS technology and integrated into the 16-line LiDAR prototype with optical components. Measurement results show that the sensor is capable of 20 m range imaging with 3 cm accuracy under 40 klux background light conditions. With the mechanical scanning system, a high-resolution image ($240\times16$) can be obtained.

In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to improve settling speed, and 1-bit redundancy is designed for calibration and dither injection. The TD-ADC with selective time domain quantization is implemented by a constant-current voltage to time converter (VTC) array and a direct positive feedback time domain comparator. The proposed VTC array can maintain high linearity with a large input swing in high-speed application. The prototype ADC was fabricated in a 28-nm CMOS process and occupied a core area of 0.074 mm2. Under a 0.95-V power supply, the chip achieves a measured peak SNDR of 53.2 dB and SFDR of 61.7 dB respectively at conversion rate up to 2.5 GS/s. The FOM is 48.2 fJ/conversion-step.

This article proposes a phase-locked loop (PLL) based on the direct digital synthesis (DDS)/digital-to-analog converter (DAC) and the double-edge zero-crossing sampling phase detector (DS-PD) for frequency-modulated continuous-wave (FMCW) radar. Its DS-PD and frequency divider are combined to achieve refined time resolution while effectively expanding the phase lock range, thus eliminating the frequency-locked loop (FLL). The DDS/DAC is used to generate FMCW signals while achieving fast frequency hopping. A differential eight switching current unit is proposed to implement an ultrahigh-speed time-interleaved DAC. The 8.55–17.11-GHz PLL prototype, fabricated in 65-nm CMOS, consumes 10.11 mW with 0.29-mm2active area, while the DDS/DAC consumes 12.0 mW with a 0.16-mm2active area. The measured in-band phase noise (PN) at a 17.11-GHz output is −120.2 dBc/Hz at a 1-MHz offset with a root-mean-square (rms) jitter of 51.7 fs. The reference spur is$3.6~\mu \text{s}$) and precise (105-kHzrms frequency error) triangular chirps for FMCW radar applications.

In this brief, a fully digitized pulse generator with programmable pulse number and width is used as an ultrawideband (UWB) pulse transmitter with 17.7-dBm output power for see-through-wall (STW) radar. A fully differential operation broadband CMOS power amplifier (PA) with a power-switchable mode and fast settling time for pulse radar is presented, achieving excellent power consumption, considerable output power, and a -3-dB bandwidth from 3.6 to 6.6 GHz. The on-chip transformer is used for impedance transformation in the output and converting signals from the differential to single ended. Fabricated in a 65-nm standard CMOS process, the operating carrier frequency range of the transmitter covers 3.2-5.8 GHz and the pulsewidth can be adjusted from 0.75 to 1.2 ns. The number of pulses varies from 4 to 1. At 10-MHz pulse repetition frequency (PRF), the maximum peak-to-peak voltage of the transmitter output pulse reaches 3.8 V with 50-Ω load, and the corresponding pulsewidth is 0.75 ns. The equivalent power is 17.7-dBm after calibration, and the average power consumption is only 22.5 mW.

In this brief, a 14-bit 500 MS/s current-steering digital-to-analog converter (DAC) is proposed, which applies the novel grouped random rotation thermometer code (GRTC) and the differential-quad switching (DQS) and has good dynamic performance without calibrations. The GRTC suppresses the harmonics caused by element mismatches, while the DQS reduces the input-code transition-dependent distortion to achieve a high spurious-free dynamic range (SFDR). A unit current cell with an intrinsic precision of 12 bits rather than 14 bits is used to reduce the active area, and the simple diagonal structure with a common-centroid layout is adopted to reduce the gradient error. The measured SFDR of the proposed DAC is more than 80 dBc below 35 MHz and better than 68 dBc over the entire Nyquist bandwidth. The power consumption of the DAC core is only 67.7 mW at 500 MS/s. The proposed DAC has been implemented in the Semiconductor Manufacturing International Corporation (SMIC) 0.18-μm CMOS process and occupies an active area of only 0.55 mm2.