A 0.52% nonlinearity,$44.9zF/\sqrt {Hz}$input capacitance noise capacitance-to-voltage (C/V) converter for MEMS accelerometer is proposed in this study. The multi-step successive approximation (SA) output mechanism is proposed to replace the conventional single-step conversion. Meanwhile, combining with the modulation-demodulation (MD) technique in the traditional continuous-time (CT) C/V converter, a much lower nonlinearity and noise CT C/V converter without increasing power consumption is achieved in this work. In addition, a short time reset signal between modulation and demodulation is proposed to reset the integration capacitors in each conversion cycle, which lets the C/V converter achieve an approximate twice dynamic range enhancement (DRE). The proposed C/V converter is implemented in a standard 180 nm CMOS process. It incorporates an on-chip capacitor signal generator (CSG), whose capacitance is tuned from −80 fF to 80 fF using clock signals at frequencies of 10Hz, 1 kHz, 2 kHz, 3 kHz, 4 kHz, and 5 kHz respectively, where measurement results demonstrate that the converter has correct output voltage across this frequency range, with a conversion error of less than$350~ppm/\sqrt {Hz}$. The proposed C/V converter is also tested together with an integrated a MEMS accelerometer element. It achieves a maximum nonlinearity as low as 0.52% within ±10 g acceleration and obtains equivalent input noise power spectral density (PSD) as low as$44.9~zF/\sqrt {Hz}$when the frequency is beyond 50 Hz.

In this paper, a bandwidth from 100Hz to 100kHz, 40dB gain filter is designed for applications where the low-frequency voltage should be reduced; while the signal should be amplified. The band-pass filter consists of a second-order high-pass filter and a capacitively-coupled chopper instrumentation amplifier (CCIA), in which the resistor of the high-pass filter adopts the current-controlled resistor technique, which greatly reduces the area compared with the traditional circuit. Simulation results show that the band pass filter can achieve effective 1/f noise suppression, reaching 74 dB common mode rejection ratio (CMRR), 73 dB power supply rejection ratio (PSRR) and 0.34% total harmonic distortion (THD) at different process angles. This is superior to other amplifiers in this frequency band.

This paper introduces a systematic approach for deriving modular multiple-input multiple-output (MIMO) converters, with the goal of simultaneously addressing challenges related to limited scalability, cross regulation, complex control, and monotonic output form. The MIMO converters are constructed using modular basic building blocks, facilitating high scalability of both the input and output ports. By carefully selecting connection styles for these building blocks, the cross-regulation issue at the output side is mitigated. This leads to a significant simplification of the control scheme. Moreover, switched resonant tanks are added to allow seamless power transition between DC and AC forms, enabling flexible output forms of MIMO converters. This feature broadens the application scenarios for the derived MIMO converters. A prototype with three output ports is built to illustrate the effectiveness of the proposed derivation methodology.

This paper presents a high-precision active-passive continuous-time Delta-Sigma Modulator (CTDSM) based on negative-R compensation technology, with a passive integrator in its first stage. Negative-R is used to alleviate the limitations of passive integrator in high-precision CTDSM applications, including integration pole drift, load effect, gain attenuation. Furthermore, in order to improve the robustness of negative-R in the integrator, an analog calibration technique is proposed. The transistor-level prototype is implemented in 180nm CMOS and the simulation results show that the proposed modulator’s signal-to-noise and distortion ratio (SNDR) is 100.2dB over a bandwidth (BW) of 24kHz, with a FoMs value of 179.4 dB.

This paper presents a continuous-time delta-sigma modulator (CTDSM) for applications that require a 5-kHz signal band and high resolution. The number of applications that use negative-R to compensate for the DC-gain, unity gain bandwidth (UGB), and noise of operational amplifiers (op-amps) is increasing. However, due to process-voltage-temperature (PVT) variations, conventional negative-R has limitations in providing ideal compensation. Therefore, this paper presents an auto-tuning (AT) negative-R that can automatically calibrate for PVT variations, overcoming the limitations caused by mismatching issues in conventional negative-R. The proposed single-bit 3rd-order CTDSM applies AT negative-R to the first integrator, resulting in consistent and optimal integrator performance. The designed CTDSM was successfully fabricated in a 28-nm CMOS process and achieved the following measurement results: a peak signal-to-noise ratio (SNR) of 92.41 dB, a peak signal-to-noise and distortion ratio (SNDR) of 90.91 dB, a dynamic range (DR) of 95 dB, total power consumption of 24$\mu$W (at a supply voltage of 1 V), and a signal bandwidth of 5 kHz.

In this paper, we present a 860.8-nW low-power third-order single-bit continuous-time delta-sigma modulator (CTDSM) for sensor applications. The proposed CTDSM decrease the power consumption of the first integrator OTA by reducing the equivalent load capacitor of the first integrator using the switched resistor technique. Unlike conventional CTDSMs, switched resistor technique can reduce the size of resistors and capacitors used as integrator coefficients by using clock duties of 25% and 75%. This method solves the problem of resistor and capacitor sizing in CTDSMs that have a low-frequency signal bandwidth. The proposed low-power CTDSM exhibits a peak signal-to-noise ratio (SNR) of 85.6 dB, a peak signal-to-noise and distortion ratio (SNDR) of 84.1 dB, and a total power consumption of 860.8 nW using a 1.6 V power supply. In addition, the simulation results revealed an SNDR of up to 84.1 dB at a sampling frequency rate of 64 kHz for a 250-Hz signal bandwidth. The circuit was designed and simulated using the$0.18-\mu\mathrm{m}$CMOS process.

With the development of mobile computing, crowd-sourcing has become one of the key technologies supporting collaborative tasks. It has been widely used in areas of real-time localization, such as data collection and fingerprint calibration. Currently, crowdsourcing-based localization are mainly designed for WiFi signals. However, due to the excellent performance on real-time positioning, Ultra-Wideband (UWB) has attracted the attention of major smart device makers. It is highly expected that UWB will be supported by smart devices in the near future. With this consideration, a crowdsourcing localization scheme is introduced based characteristics of UWB signals. Compared to existing positioning technologies, the proposed scheme does not require direct connection between UWB anchors and smart devices. Instead, the smart devices collaborate with peers to complete the positioning process. Finally, a simulation example is provided as a demonstration and to evaluate the performance.

In smart grid, demand-side communications play a significant role in real-time applications, such as demand response and advanced metering. With recent progresses on Internet-of- Things (IoTs), different communication technologies are available for the demand side, such as ZigBee, Bluetooth, Wi-Fi, etc. To improve the inter-operability of various IoTs in demand side of smart grid, ZigBee and Homeplug Alliances have jointly developed the Smart Energy Profile 2.0 (SEP 2.0)as the upper-layer communication protocol, which has been approved as an international standard, namely IEEE 2030.5. Despite of its promising application in demand side, the development on constrained IoT devices is challenging. To address this issue, an upper middleware for SEP 2.0 standard is developed based on the SimpleLink Wi- Fi technology of Texas Instruments (TI). It enables SimpleLink Wi-Fi devices to support SEP 2.0-based communications in the demand side of smart grid. In the end, an experimental system is built to demonstrate the effectiveness of the presented upper middleware.