This paper presents a comprehensive compliance framework for RISC-V architectures and the benefit of the RISCOF test platform. The framework aims to ensure that RISC-V implementations, whether hardware or software, adhere to established specifications, and this framework has the flexibility and scalability for future extensions and updates in the RISC-V ecosystem. By utilizing a structured approach, the framework integrates various testing components to evaluate compliance effectively. Key features include the generation of targeted tests based on specific architecture profiles and the ability to assess both functional and performance aspects of implementations. The framework is designed to be flexible and scalable, accommodating future extensions and updates in the RISC-V ecosystem. Through rigorous testing and validation processes, it provides developers with essential tools to verify their designs against compliance standards. This work contributes to the growing body of knowledge in RISC-V architecture by offering a systematic method for ensuring compatibility and reliability across different implementations. Ultimately, this framework serves as a vital resource for engineers seeking to enhance the quality and integrity of RISC-V products in the market.

Hardware accelerators outperform CPUs in terms of performance by parallelizing the algorithm architecture and using the device’s programmable resources. FPGA is a type of hardware accelerator that excels not only in performance but also in energy efficiency. So, it provides a suitable platform for implementing complicated fractional-order systems. This paper proposes a novel phase-based optimization method to implement fractional operators using FIR and IIR filters. We also compare five fractional operator implementation methods on FPGA regarding resource utilization, execution time, power, and accuracy. These methods and the proposed one are evaluated in terms of power consumption, delay, and resources to assist the designer in determining the most suitable implementation method for the given application. The proposed method has a lower phase error of 14.7% in the case of derivative operation and a lower phase error of 18.83% in the case of integration compared to the literature. In addition, the proposed methods decreased the consumed power and area by more than three times compared to the fixed-window GL fractional operator. The proposed approach implements Heaviside’s inductor-terminated lossy line. In addition, it is employed as an edge detection kernel to demonstrate its effectiveness in image processing applications.

Multipliers are a major energy and delay contributor in modern compute-intensive applications due to their complex logic architecture. As such, designing multipliers with reduced energy and faster speed has remained a thoroughgoing challenge. This paper presents a novel, carry-free multiplier, which is suitable for a new-generation of energy-constrained applications. The multiplier circuit consists of an array of memristor-transistor cells that can be selected (i.e., turned ON or OFF) using a combination of DC bias voltages based on the operand values. When a cell is selected it contributes to current in the array path, which is then amplified by current mirrors with variable transistor gate sizes. The different current paths are connected to a node for analogously accumulating the currents to produce the multiplier output directly. This removes the need for latency-sensitive carry propagation stages, typically seen in traditional multipliers. We conduct a number of experiments to validate the functional and parametric properties. Our experiments showed that proposed multiplier achieves 51.44% savings in energy at a similar accuracy when compared with recently proposed approaches.

Memristors are intensively proposed in many applications, such as biosensors and machine learning. Regarding their analog characteristics, memristance decoder is, therefore, an essential part for every memristor-based system. As memristor is a temperature sensitive device, this work proposes a memristance decoder circuit with self-temperature calibration. Its main building block is a comparator which is based on current mode circuit to achieve high performance at low power. The design provides configurable precision based on the available energy and supports both synchronous and asynchronous schemes. Moreover, the VTEAM model is modified to include the temperature effect on the memristance in the analysis. The simulation results, based on UMC 65nm low-leakage CMOS technology, show the following comparator's characteristics: 1.70% maximum offset, 2.91ns worst case latency, 343MHz maximum frequency and 48.79fJ maximum energy per comparison. Monte Carlo simulation shows the metastable state in determining the memristor value. This can be solved by extending the clock period or applying a metastability resolver. The proposed memristor model reveals that memristance at high resistive state degrades quadratically with the rise of the temperature and at 85C nearly reaches the memristance of low resistive state.

Nowadays, the interconnect circuits' conduct plays a crucial role in determining the performance of the CMOS systems, especially those related to nano-scale technology. Modeling the effect of such an influential component has been widely studied from many perspectives. In this article, we propose a new general formula for RLC interconnect circuit model in CMOS technology using the fractional-order elements approach. The study is based on approximating an infinite transfer function of the CMOS circuit with a noninteger distributed RLC load to a finite number of poles. It is accurate due to the effect of adding fractional-order variables and since these variables are utilized for tuning the model to match the design regardless of its complexity. As such, delay calculations employing our analytical model are within 0.4 absolute error of COMSOL-computed delay across a range of interconnect lengths. Furthermore, the effect of the interconnect conductivity G has been taken into account tacitly although the model included the resistance R, inductance L, and capacitance C of the interconnect. A number of analyses were set up at different levels of the design to evaluate the effectiveness. First, demonstrating the significant effects of generalizing parameters was gained by studying the fractional-order impedance and propagation constant of the transmission line for a range of frequencies. Second, using MATLAB we assessed the potential of the proposed approximated model besides the exact one, which shows similarity in the fundamental features of the system, such as stability and resonance. Third, the proposed approach showed that with a very small tuning reach 0.01 of the generalizing parameters can achieve up to 15% improvement in the model accuracy.

In this paper, we present a reprogrammable low power optogenetic based platform for closed-loop processing, which aims on neural abnormal activity invention such as epilepsy. The system is comprised of an embedded control system, and a custom designed ASIC chip for electrical recording and optical stimulation. Compared to current technologies, developed technology is not only show ultra-low power consumptions but also displays strong computational flexibility. A power cycling technique was implemented, which reduces the average power consumption of the system down to 2.93 mA at recording frequency 50Hz (equal to ASIC level). This allows a system lifetime up to 56 hours with a single Lithium-Polymer battery (165mAh). Then a three-stage closed-loop processing scheme is employed to foster a Brain-machine Interface (BMI) tool box, which allows the system meets various biomedical application requirements. By using in-vivo epilepsy neural data, our system demonstrates the capability for realtime intervention of abnormal activities. Hence, the developed technology shows great potential for both rodent behavior control based and implantable electronics applications such as chest units.

More than a decade has passed since optics and genetics came together and lead to the emerging technologies of optogenetics. The advent of light-sensitive opsins made it possible to optically trigger the neurons into activation or inhibition by using visible light. In this work we integrated virtual reality optical system with a high radiance high density microdisplay to implement a wearable device for Retinitis Pigmentosa (RP) patients. We built system to emulate the human eye and light attenuation while it passes through the eye to the retina. The average light intensity on the surface of the retina after the optical system is 1.35mW/mm2which is above the ChR-2 stimulation level (0.7mW/mm2). The number of pixels which give light intensity above the stimulation threshold is 7128 pixel out of 8100 pixel in the microdisplay. The average efficiency of the optical system is 5.75%. So, the proposed wearable device will be able to restore vision for RP patients without the need for invasive implantable device by using optogenetics stimulation.

In this work, we present an analytical approach of closed-loop Proportional-Derivative (PD) control to determine the stimulation parameters for suppressing high-amplitude epileptic activity in a neural mass model. Closed-loop PD control to suppress epileptic activity in the Jansen's neural mass model (Jansen's NMM) has been studied. This work shows that the output signal of the Jansen's NMM model without the PD control feedback is high amplitude epileptic seizure activity which turns into low amplitude activity with the intervention feedback of a PD controller. A graphical stability analysis method was employed to determine the stability region of the PD controller in the gain parameter space. Therefore, this approach draws a region of PD controller parameters that is empirically chosen to stabilize epileptic seizure activities in the chosen NMM. Furthermore, this approach allows us to explore the relationship between the model parameters of inducing epileptic activity and the feedback controller parameters to foster a better understanding of the mechanism to suppress epileptic seizure activity by applying closed-loop stimulation (pharmacology stimulation, electrical stimulation or optogenetic stimulation etc.).

This paper presents a way to realize a simple yet accurate excitation time model of memristor-based circuits that are in the form of voltage dividers. According to the supported circuit structure, this model is compatible with a wide range of memristor applications, such as delay elements and analog memories. Memristance tuning based on excitation time estimation, i.e. pulse width, instead of using comparators, helps to save area and power. A general-purpose memristance tuning (GMET) circuit is proposed in order to demonstrate the simplicity of the proposed model and to evaluate its accuracy. Our model estimates are compared against the simulation results for the GMET circuit with VTEAM model of the memristor. The results show that the whole-range memristance shifts can be estimated with the worst case average error of 5.49%. They also show the worst case maximum error of 13.25%, which reduces to less than 7% when the operated memristance is higher than 2.5kΩ.

A detachable Flash-FPGA based rodent control system implementation of seizure detection algorithm and following closed-loop optogenetic stimulation will be reported in this work. The proposed detachable Flash-FPGA system receives incoming local field potential recordings of target neurons, and extracts seizure feature pattern in specific frequency band by applying wavelet filter for a further threshold comparison of seizure detection. If the wavelet filter output is above the threshold, the system determines the incoming signal is seizure and then optogenetic stimulus will be triggered as a delivery to target neurons for suppressing seizures. Taking advantage of Flash-FPGA platform, a minimal detection delay of 0.575 ms has been achieved. The tested power consumption of seizure detection implementation in Flash FPGA costs 0.168 mW which represents the seizure detector can run on a wearable battery cell for more than 20 years.