EDBT 2026 Demo / reviewers in the wild / expert
You You
dblp:159/4412
· DBLP profile ↗
12ranked-venue papers
4as first author
8since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 1 first-author · 4 since 2021Computer networks · 3 · 3 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 3 · 2 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | TIP: Turbo Implicit Pursuit Channel Estimator for mmWave MIMO SystemsabstractCompressed-sensing (CS)-based channel estimation is a promising technology for future millimeter wave (mmWave) multiple-input–multiple-output (MIMO) systems, enabling significant pilot reduction and improved estimation accuracy. Channel estimators based on matching pursuit (MP) variants offer lower complexity compared with other CS algorithms, but suffer from high latency due to their iterative nature, hindering efficient hardware implementation. To mitigate this issue, this article introduces a turbo pursuit (TP) strategy that relaxes sequential dependencies in MP variants, enabling parallel processing and pipelined implementation. To demonstrate the effectiveness of TP, this article further introduces turbo implicit pursuit (TIP), a hardware-friendly instance of TP that leverages a prioritized gradient descent (GD) strategy for low-complexity least squares (LS) solving. A hardware auto-generator for TIP is then proposed using a formula representation approach, which constructs a parameterized hardware-algorithm design space and enables hardware-algorithm co-optimization. Our optimized$32 \times 4$TIP MIMO channel estimator ASIC in 65-nm CMOS achieves 0.53-$\mu $s latency under 18.75% measurements. Compared with prior implementations of MP variants, this work achieves higher or comparable estimation accuracy with over 18% latency reduction and over 5$\times$higher throughput to area ratio (TAR) for ASICs, and over 90% latency reduction with over 3$\times$higher hardware efficiency for FPGAs. Changhan Li, Xingchi Zhang, Yutai Sun, Yunwei Mao, Yifang Dai, You You, Yongming Huang 0001, Chuan Zhang 0001 |
IEEE Trans. Very Large Scale Integr. Syst. | 6 |
| 2025 | Fast construction and exploration of performance-cost design space for belief propagation polar decoders
You You, Weikang Qian, Yongming Huang 0001, Chuan Zhang 0001 |
Sci. China Inf. Sci. | 2 |
| 2025 | Toward mobile communication baseband circuit auto-design: a Bayesian model approach
Chuan Zhang 0001, Changhan Li, Yunwei Mao, Yuwei Zeng, You You, Yongming Huang 0001, Xiaohu You 0001 |
Sci. China Inf. Sci. | 6 |
| 2025 | Adaptive Channel Estimation for RIS-Assisted Systems in Time-Varying mmWave ChannelsabstractTo improve channel estimation (CE) for reconfigurable intelligent surface (RIS)-assisted systems in time-varying mmWave channels, this paper proposes a two-stage adaptive CE scheme. This is the first attempt to develop a CE scheme without assumptions on specific timescales for channel variations. In the first stage, the adaptive scheme incorporates the estimation of partial channel state information and a channel status check process. The introduced check process can monitor the changing status of the channels and provide information for the second stage. In the second stage, based on the results from the check process, the adaptive scheme adaptively selects from two proposed candidate CE algorithms: Two-Phase orthogonal matching pursuit (TP-OMP) and Structured-Shift OMP (SS-OMP). Simulation results show that both TP-OMP and SS-OMP can reduce pilot overhead by around 33%, and respectively lower the computational complexity of existing works by about 55% and 65%. Additionally, the check process obtains an accuracy rate of approximately 92% so that the proposed CE scheme can maintain stable CE performance in time-varying channels. You You, Fengyu Chen, Li Zhang 0011, Yongming Huang 0001, Chuan Zhang 0001 |
IEEE Trans. Commun. | 1 |
| 2024 | FLAG: Formula-LLM-Based Auto-Generator for Baseband Hardware
Yunwei Mao, You You, Xiaosi Tan, Yongming Huang 0001, Xiaohu You 0001, Chuan Zhang 0001 |
ISCAS | 2 |
| 2024 | A 27.5 fJ/step SAR Capacitance-to-Digital Converter Based on Correlated Double SamplingabstractThis paper presents a low-power and energy-efficient capacitance-to-digital converter (CDC) for a single-end sensor based on correlated double sampling (CDS) technology. The CDS is accomplished by two opposite conversions, which reuse the comparator, CSENS, and CDAC. The proposed CDC eliminates the parasitic-dependent error caused by the comparator’s offset without extra consumption through the CDS. The simulation results show that the CDC can eliminate low-frequency interference and achieve anti-common-mode interference capabilities similar to differential circuits. To achieve low noise and high energy efficiency, the CDC employs a floating inverter amplifier (FIA) as the pre-amplifier of the comparator. Implemented in a 0.18 μm CMOS process, it consumes 0.91 μW from a 1.2 V supply. The simulation results show an effective number of 11.69 bits and an energy efficiency of 27.5 fJ per conversion step. Qingjiang Xia, You You, Yacong Zhang, Wengao Lu, Runkun Zhu, Zhongjian Chen |
ISCAS | 2 |
| 2023 | A 10-Bit 15 V-Compliant Bi-Phasic Current-Mode Vagus Nerve Stimulation Circuit in 180 nm BCD TechnologyabstractThis work presents an application specific integrated circuit (ASIC) working as an electrical vagus nerve stimulation (VNS) system targeting emerging VNS-based point-of-care treatments where such a system needs to be implanted within the human body. Implemented in a 180 nm Bipolar-CMOS-DMOS (BCD) process, the ASIC is capable of delivering accurate stimulation current, and can support stimulation voltages up to 15 V. Such a high voltage compatibility provides extra room for variances in tissue impedance under the same requested stimulation current. The design is tested with a commercial-grade platinum helical electrode, and shows a maximum output current of 7 mA when the electrode is submerged in phosphate-buffered saline (PBS), and a low standby power of$9.63\ \mu\mathrm{W}$. The low power, small area, high output current resolution, and process's compatibility with direct processor integration all make this design a promising candidate for a single-chip implanted VNS system. You You, Kangwei Ma, Ruizhi Tian, Yacong Zhang, Zhongjian Chen, Yihan Zhang 0002 |
ISCAS | 1 |
| 2022 | Exploiting angular spread in channel estimation of millimeter wave MIMO systemabstractAbstract Millimeter wave (mmWave) frequency spectrum can mitigate severe spectrum shortage caused by the explosive growth of mobile data demand. To overcome the high propagation loss of mmWave signals, massive multi‐input multi‐output (MIMO) and hybrid architecture are employed. As in microwave communication systems, channel state information (CSI) is essential to fully achieve the advantages of mmWave communication. However, due to the massive number of antennas and hybrid architecture, the CSI acquisition is challenging. The sparsity of mmWave channel can be utilized to reduce the training overhead. In addition to sparsity, real‐world measurements in dense urban propagation environments reveal that the mmWave channel may spread in form of cluster of paths over the angular domains, namely the angular spread. In this paper, it is utilized to formulate the channel estimation as a block‐sparse signal recovery problem. The block orthogonal matching pursuit (BOMP) is used to validate the model. Then, block fast Bayesian matching pursuit (BFBMP) algorithm is proposed to solve the above problem. Compared with other existing channel estimation methods, simulation results show that the angular spread feature and the proposed BFBMP can considerably improve the CSI estimation with less complexity. You You, Li Zhang 0011 |
IET Commun. | 1 |
| 2019 | A 16-bit 64-channel 2-order Incremental Σ-Δ ADC with On-Chip Decimator for X-ray DetectionsabstractThis paper presents a 16-bit 64-channel 2-order incremental Σ-Δ ADC with an on-chip decimating filter for linear X-ray detector array. In order to achieve high-resolution and multi-channel integration, a series of coefficients for a 2-order Σ-Δ modulator are optimally designed which are based on time-domain relationship between the modulator input and output. Therefore, a decimating filter consists of only a counter and an integrator can be used to acquire Nyquist rate output. A residual error reduction method at the end of each conversion period is also proposed to refine the resolution of convertor by extending several clock cycles and reusing the same circuit modules. As a result, a high-resolution, small area cost and power efficient readout interface circuit (ROIC) is achieved. A prototype chip is designed in 0.18μm CMOS process. Simulation results reveal the ADC achieves ±0.5 LSB quantization error and 91.4 dB SNR within 1.9 kHz bandwidth, meanwhile, area of the decimating filter in single channel is only 42×90 μm2. You You, Wengao Lu, Xueyou Shi, Zhongjian Chen, Yacong Zhang |
ISCAS | 2 |
| 2019 | Joint Power and Channel Allocation for Underlay D2D Communications with Proportional FairnessabstractSince D2D (Device-to-Device) communication was proposed in cellular network as a new paradigm for enhancing network performance, many works have been done on resource allocation to improve system throughput and energy efficiency (EE) for underlay D2D communications. However, the system long-term average fairness as one of the system main performance metrics was rarely considered especially when users are moving. In this paper, we formulate the joint power and channel allocation problem aiming at maximizing the system fairness subject to the minimum required SINRs (Signal to Interference and Noise Ratios) and power consumption limits of cellular and active D2D links. To solve the above problem practically, we first decompose our original problem into two sub-problems (power and channel allocation), then solve them sequentially. Simulation results show that our proposed algorithm can dramatically enhance the system fairness and slightly improve the system throughput comparing with existing method. Miaomiao Liu 0002, Li Zhang 0011, You You |
IWCMC | 3 |
| 2019 | IP Aided OMP Based Channel Estimation for Millimeter Wave Massive MIMO CommunicationabstractAdoption of hybrid precoding is the key element of reducing the hardware cost of radio-frequency compared with the conventional full-digital precoding approach in millimeter wave (mmWave) MIMO systems. For hybrid precoding, channel state information (CSI) is needed. However, the use of analog precoding in hybrid architecture and the large antenna array make channel estimation difficult for mmWave system. It has been shown that mmWave channels exhibit sparsity, thus compressive sensing (CS) techniques can be leveraged to conduct channel estimation. Conventional CS based channel estimation methods for mmWave MIMO are based on quantized angle grid. However, the performance would be severely affected by off grid angles which can not be improved by increasing the resolution because this will increase the coherence between the grid points. In this paper, we propose an Interior Point (IP) aided orthogonal matching pursuit (OMP) algorithm. It significantly improves the channel estimation accuracy by reducing the estimation error of angle-of-departure (AoD) and angle-of-arrival (AoA). The simulation results demonstrate the advantage of the proposed IP-OMP over the existing methods such as least squares and the conventional OMP. You You, Li Zhang 0011, Miaomiao Liu 0002 |
WCNC | 1 |
| 2017 | Compressed sensing-based time-domain channel estimator for full-duplex OFDM systems with IQ-imbalances
Hai Yu 0006, Feng Shu 0002, You You, Jin Wang 0020, Tingting Liu 0005, Xiaohu You 0001, Jinhui Lu, Jianxin Wang 0002 |
Sci. China Inf. Sci. | 3 |