Simulation-based verification of Very-Large-Scale Integration (VLSI) chip design is inevitable. However, the simulation speed can be a bottleneck in the verification process productivity. People tried to accelerate simulation-based verification through parallelization, emulation, and reducing the number of test scenarios, etc. In this paper, we exploited the power of abstraction of SystemC to design fast and accurate golden functional reference models. These reference models can be integrated in the Universal Verification Methodology (UVM) based TestBench through Transaction Level Modeling (TLM). Thus, the UVM based TestBench interacts with the SystemC reference model to get the golden values, and use them for checking. We used the proposed methodology to verify the execution unit (EXU) of the open-source RISC-V based VeeR EL2 processor core. The experimental results showed that the proposed TestBench architecture with SystemC reference model is up to 15x faster than the TestBench with SystemVerilog reference model.

Requiring no functional simulation, trace-driven simulation has the potential of achieving faster simulation speeds than execution-driven simulation of multicore architectures. An efficient, on-the-fly, high-fidelity trace generation method for multithreaded applications is reported. The generated trace is encoded in an instruction-like binary format that can be directly “interpreted” by a timing simulator to simulate a general load/store or x8-like architecture. A complete tool suite that has been developed and used for evaluation of the proposed method showed that it produces smaller traces over existing trace compression methods while retaining good fidelity including all threading- and synchronization-related events.

Simulation is the main tool for computer architects and parallel application developers for developing new architectures and parallel algorithms on many-core machines. Simulating a many-core architecture represent a challenge to software simulators even with parallelization of these SW on multi-cores. Field Programmable Gate Arrays offer an excellent implementation platform due to inherent parallelism. Existing FPGA-based simulators however, are mostly execution-driven which consumes too many FPGA resources. Hence, they still trade-off accuracy with simulation speed as SW simulators do. In this work, an application-level trace-driven FPGA-based many-core simulator is presented. A parameterized Verilog template was developed that can generate any number of simulator tiles. The input trace has an architecturally agnostic format that is directly interpreted by the FPGA-based timing model to re-construct the execution events of the original application with accurate timing. This allows fitting a large number of simulation tiles on a single FPGA without sacrificing simulation speed or accuracy. Experimental results show that the simulator's average accuracy is ~14 percent with simulation speeds ranging from 100's of MIPs to over 2,200 MIPS for a 16-core target architecture. Hence, with accuracy similar to SW simulators, its speed is higher than all other FPGA-based simulators.