This work presents a single-stage operational transconductance amplifier (OTA) with high DC gain for driving nano-farad capacitive loads. The circuit employs two conjugated current mirrors to form high-impedance nodes, enhancing transconductance and driving capability. Flipped-voltage follower (FVF) cells act as variable tail current sources to boost transconductance and generate a dynamic current larger than the bias current during slewing, enabling a faster transient response. The FVFs also allow additional folded drivers on the cascode stage for further improvement. To integrate these techniques, both n- and p-channel differential pairs are used at the input. Implemented in TSMC 0.18-μm CMOS, the OTA achieved a simulated DC gain above 100 dB and a measured gain of 95 dB, validating the proposed design. It shows a unity-gain bandwidth of 5.85 MHz and a slew rate of 0.347 V/μs while driving a 2×4 nF load at 1.8 V.

This work presents an ultralow-voltage and ultralow-power current-mode delta-sigma modulator designed for biomedical applications. To implement both the integrator and quantizer of the modulator, a bulk-driven current conveyor circuit is introduced. By satisfying the Barkhausen criterion, the proposed modulator can intrinsically oscillate, producing a pulse-density modulated (PDM) output. This clock-less operation avoids conventional quantization noise associated with discrete-time sampling. The current-mode design not only provides improved matching properties and a wider bandwidth but also simplifies the implementation of passive components, resulting in a smaller silicon area compared to voltage-mode modulators—though this area efficiency is partly achieved using off-chip components. The circuit has been fabricated using standard TSMC 0.18-$\mu $m CMOS technology, occupying a silicon area of$226~\mu $m×$264~\mu $m. Despite consuming only 34 nW of power, experimental results demonstrate a signal-to-noise and distortion ratio of 57.1 dB, corresponding to an effective resolution of 9.2bits with a bandwidth of 81 Hz. Additionally, the use of the bulk-driven method achieves an input dynamic range of ±24nA under a supply voltage of 0.3 V.

This paper presents a chopper-stabilized three-stage operational amplifier (OpAmp) with a unity gain bandwidth of 69 MHz and an input referred noise density of 3 nV$/\surd{Hz}$. The proposed design achieves a stable unity gain by proposing a new pole and zero scheme with very low power consumption, drawing only 3.3 mA from a 1.8 V power supply while driving a load capacitor as large as 100pF. To achieve rail-to-rail input swing, the design uses both NMOS and PMOS differential pairs at the input and biases them in the subthreshold region to provide an identical net trans-conductance over the rail-to-rail input common mode. Furthermore, an adaptive biasing is employed and the current sources are kept ON during large signal transitions at the input, thus eliminating crossover distortion and providing a high slew rate of 40 V/$\mu$s at a 100 pF load capacitor. The design employs chopping at 2.5 MHz and is enhanced with a local ripple reduction loop, making the OpAmp suitable for high gain and wide bandwidth applications with less filtering required. The design also reduces the input bias current significantly from 500 nA to 1.5 nA by buffering the input and applying it to the modified bootstrap switches. The proposed OpAmp, fabricated in a 0.18$\mu$m CMOS process, exhibits a maximum offset of 4.5$\mu$V, a flicker noise corner frequency of 246 Hz, a DC gain of 146 dB, a power supply rejection ratio of 123 dB, and a common mode rejection ratio of 116 dB.

This work presents a general enhancement in operational transconductance amplifiers (OTAs) by conjugating the diode-connected topologies of the current mirrors (CMs). The proposed conjugation method provides an internal high-impedance node, by which the transconductance of the amplifier is significantly increased. Since the central node of the conjugated CMs is virtually grounded for small differential signals, the cascode devices of the diode-connected topologies can be employed as an extra differential pair causing a further enhancement in transconductance. Moreover, the large signal behavior of the circuit shows that the conjugated CMs are capable of copying a dynamic current with a higher gain in comparison with a traditional CM amplifier. This advantage results in faster charging and discharging of the output capacitive load, which provides a larger slew rate (SR) without increasing the quiescent current. The proposed amplifier was manufactured with TSMC 0.18-$\mu $m CMOS technology occupying a silicon area of$55.5\times 48.9~\mu $m. Experimental results at a supply voltage of 1.8 V show a gain bandwidth (GBW) of 104.9 MHz, a dc gain of 79.1 dB, and an SR of 55.7 V/$\mu $s for a capacitive load of 10 pF, while the circuit consumes 489-$\mu $W power.

This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.5\times 30.1\,\,\mu \text{m}$. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/$\mu \text{s}$for a capacitive load of$2\times5$pF. The proposed circuit consumes 619$\mu \text{W}$of power, under a supply voltage of 1.8 V.

In this brief, two current generator circuits are used to design a self-biasing transconductance amplifier. The current generators are configured using two n-channel and p-channel cascode current mirrors by which a high input dynamic range is achieved. Since such a topology creates positive feedback, the transconductance of the circuit is also increased causing higher performance. To ensure the stability of the circuit, constant current sources can be paralleled with the current mirror topologies, which of course are implemented using input drivers. Therefore, two n-channel and p-channel input differential pairs are added to the current generator circuits by which not only a rail-to-rail operation is achieved but also the amplifier is stabilized. The proposed circuit was fabricated in the TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.1\times 71\,\,\mu \text{m}$. Under a 1.8-V supply voltage, the experimental results showed a high input common-mode range (ICMR), while a gain bandwidth (GBW) of 83.9 MHz was measured for a capacitive load of$2\times6$pF. In addition, a dc gain and a slew rate (SR) of 68.4 dB and 71.7 V/$\mu \text{s}$, respectively, were achieved.

This work presents a tail-less fully differential bulk-driven transconductance amplifier without using a common-mode feedback (CMFB) circuit. The proposed amplifier employs two P-type and N-type current mirrors to form two self-biasing positive feedback loops resulting in a double transconductance. The bulk terminals of the P-type current mirrors are used as the input nodes to provide a high input dynamic range. The diode-connected topologies of the current mirrors adaptively bias other transistors to cover the lack of the CMFB circuit. To ensure stability, additional current sources are paralleled with the positive feedback structures. A high output voltage swing and a high DC gain are achieved by adding an adaptively biased common-source amplifier as the output stage leading to a class-AB operation. A large signal analysis, in weak inversion, is also done to mathematically describe both small- and large-signal characteristics. The proposed circuit was fabricated using TSMC$0.18 \mu \text{m}$CMOS technology occupying a silicon area of$113\,\,\mu \text{m}\,\,\times 70\,\,\mu \text{m}$. Experimental results at a supply voltage of 0.4 V show a gain bandwidth of 7 kHz, a DC gain of 60 dB, and a slew rate of 79 V/ms with just 24 nW power dissipation while driving a capacitive load of$2\times 15$pF.

This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, the circuit employs three linearization techniques: the bulk-driven (BD), the source degeneration, and the input voltage attenuation created by the MI metal-oxide-semiconductor transistor technique (MI-MOST). Although the linearization techniques result in reduced dc gain, the self-cascode transistors are used to boost the gain of the MI-OTA. Furthermore, the MI-MOST simplifies the internal structure of the OTA and may reduce the complexity of the applications. The MI-OTA operates in the subthreshold region and offers tunability by a bias current in the nanoampere range. The circuit is capable to work with 0.5-V supply voltage while consuming 24.77 nW. The circuit was fabricated using the 0.18-$\mu \text{m}$Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology and it occupies a 0.01153-mm2 silicon area. Intensive simulation and experimental results confirm the benefits and robustness of the design.

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier's specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18- μm CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.

A high slew rate operational transconductance amplifier (OTA) based on the dynamic current boosting paths is presented. Two flipped voltage-follower (FVF) cells adaptively bias the input drivers and provide a class AB operation with capability of adding new input to output paths. In addition to the reduction of the settling time of the step response, these paths operate as new drivers that increase the small signal transconductance of the proposed amplifier. Simulation results in a TSMC 90 nm complementary metal oxide semiconductor (CMOS) technology show an 83 % decrease in the settling time and a 14.5 dB increase in the DC gain of the proposed class AB amplifier versus the conventional class A amplifier.