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Suzana Milutinovic

dblp:159/8510 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 2019
0000-0003-2429-0949ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Embedded and real-time systems · 72% Memory systems · 23% Performance modeling and evaluation · 5%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Embedded and real-time systems
worst-case execution time analysis
0.932019
Increasing the Reliability of Software Timing Analysis for Cache-Based Processors · IEEE Trans. Computers 2019
Measurement-based cache representativeness on multipath programs · DAC 2018
PACO: fast average-performance estimation for time-randomized caches · DAC 2015
Embedded and real-time systems
real-time scheduling
0.522018
Measurement-based cache representativeness on multipath programs · DAC 2018
PACO: fast average-performance estimation for time-randomized caches · DAC 2015
Memory systems
cache
0.532019
Increasing the Reliability of Software Timing Analysis for Cache-Based Processors · IEEE Trans. Computers 2019
Measurement-based cache representativeness on multipath programs · DAC 2018
PACO: fast average-performance estimation for time-randomized caches · DAC 2015
Embedded and real-time systems › real-time scheduling
probabilistic timing analysis
0.212015
PACO: fast average-performance estimation for time-randomized caches · DAC 2015

Methods — techniques the papers use, named apart from their topics

probabilistic timing analysis · 0.6random modulo · 0.4hash-based random placement · 0.4measurement-based timing analysis · 0.3
YearPublicationVenuePosition
2019 Increasing the Reliability of Software Timing Analysis for Cache-Based Processors
abstract
Real-time systems are witnessing a significant increase in critical software's size, complexity, and performance needs, which can only be satisfied with high-performance hardware features. Cache memories, pervasively used to improve average performance, complicate Worst-Case Execution Time analysis: cache placement (i.e., how software objects are mapped to cache) during the testing phase does not only critically affect the observed performance, but also proves to be arduous to control and preserve up to operation. The probabilistic variant of Measurement-Based Timing Analysis (MBPTA) responds to this challenge by deploying time-randomized caches that naturally explore a different random cache placement in each run, relieving the user from producing tests that intercept relevant Cache Conflict Placements (CCP). Yet, to meet an adequate probabilistic CCP coverage, the user is required to collect a minimum number of measurements. We present two mechanisms, CCP-RM and CCP-HRP, to identify CCP with relevant probability of occurrence and large impact on execution-time, for the random modulo (RM) and hash-based random placement (HRP) policies. CCP-RM and CCP-HRP enable a reliable application of MBPTA by computing the number of runsR' necessary to meet the desired CCP coverage. We exhaustively evaluate CCP-RM and CCP-HRP, showing their effectiveness on well-known benchmarks and a railway case study, on top of an accurate simulator and a concrete RTL implementation.
Suzana Milutinovic, Enrico Mezzetti, Jaume Abella 0001, Francisco J. Cazorla
IEEE Trans. Computers1
2018 Measurement-based cache representativeness on multipath programs
abstract
Autonomous vehicles in embedded real-time systems increase critical-software size and complexity whose performance needs are covered with high-performance hardware features like caches, which however hampers obtaining WCET estimates that hold valid for all program execution paths. This requires assessing that all cache layouts have been properly factored in the WCET process. For measurement-based timing analysis, the most common analysis method, we provide a solution to achieve cache representativeness and full path coverage: we create a modified program for analysis purposes where cache impact is upper-bounded across any path, and derive the minimum number of runs required to capture in the test campaign cache layouts resulting in high execution times.
Suzana Milutinovic, Jaume Abella 0001, Enrico Mezzetti, Francisco J. Cazorla
DAC1
2016 Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns
abstract
Measurement-Based Probabilistic Timing Analysis (MBPTA) is a promising powerful industry-friendly method to derive worst-case execution time (WCET) estimates as needed for critical real-time embedded systems. MBPTA performs several (R) runs of the program on the target platform collecting the execution times in each run. MBPTA builds a probabilistic representativeness argument on whether those events with high impact on execution time, such as cache misses, arise on the runs made at analysis time so that their impact on execution time is captured. So far only events occurring in cache memories have been shown to challenge providing such representativeness argument. In this context, this paper introduces a representativeness validation method (RVS) to assess the probabilistic representativeness of MBPTA's execution time observations in terms of cache behaviour. RVS resorts to cache simulation to predict worst-case miss scenarios that can appear during the deployment phase. RVS also constructs a probabilistic Worst-Case Miss Count curve based on the miss-counts captured in the R runs. If that curve upperbounds the impact of the predicted cache worst-case scenarios, R is deemed as a sufficient number of runs for which pWCET estimates can be reliably derived. Otherwise, the user is requested to perform more runs until all cache scenarios of interest are captured.
Suzana Milutinovic, Jaume Abella 0001, Francisco J. Cazorla
ISORC1
2015 PACO: fast average-performance estimation for time-randomized caches
abstract
Probabilistic timing analysis is a powerful approach to derive worst-case execution time (WCET) estimates, as needed in safety-critical systems, in the presence of high-performance hardware features (e.g., caches). To that end, the timing behavior of certain hardware resources, such as caches, is randomized. Time-randomized (TR) caches allow deriving hit/miss probabilities for each access and probabilistic WCET estimates for the overall program.
Suzana Milutinovic, Eduardo Quiñones, Jaume Abella 0001, Francisco J. Cazorla
DAC1