The widespread application of specialized embedded devices and their ever-growing sensing capabilities lead to an overload of raw data reaching the Cloud via the Internet of Things. Despite this massive amount of available data, data-driven applications still produce a limited impact on the real world. We argue that this limitation arises from the complexity the developers still face when engineering and deploying solutions on a plurality of embedded devices. Instead of focusing on constructing valuable information from raw data and designing algorithms to exploit it, the developers still have to figure out on their own: how to partition the computation between Edge, Fog, and Cloud; how to move partial results around in highly distributed solutions; how to create abstract interfaces to expose information-rich endpoints. This paper introduces the Virtual Sensor Domain-Specific Language (DSL), which builds the keystone for designing and developing powerful Computer-Aided Design tools and Integrated Development Environments to support the developers in focusing on information manipulation. The Virtual Sensor DSL is built on top of C++ to ease its adoption by the embedded development community. It introduces a reactive approach to data collection, technology mapping, and workload distribution. It allows the creation of adaptable Virtual Sensors, streaming processed information coming from the integration of multiple raw data streams, and it comes with integrated simulation capabilities, supporting prototyping. In this paper, we describe the entities the language offers, how the developers can exploit them, and analyze a real-world use case that benefitted from the Virtual Sensor DSL.

With reconfigurable fabrics delivering increasing performance over the years, Field-Programmable Gate Arrays (FPGAs) are becoming an appealing solution for next-generation High-Performance Computing (HPC) systems. However, in order to gain traction among traditional von Neumann architectures, the optimization process of Field-Programmable Gate Array (FPGA) designs should be further abstracted to a higher level. In fact, while High-Level Synthesis (HLS) already provides a handy way to write FPGA code with common high-level languages, substantial effort and expertise are still required to optimize the resulting FPGA design for the underlying hardware. To overcome this problem, we propose a semi-automated performance optimization methodology based on a Hierarchical Roofline model for FPGAs. System-wide and applications-specific optimizations such as off-chip memory transfer and data locality optimizations are guided by the FPGA Roofline model whereas FPGA-specific optimizations are automatically searched by a Design Space Exploration (DSE) engine. We demonstrate the way this methodology allows to easily analyze and optimize to peak system performance a wide set of applications ranging from particle methods, wavefront algorithms, and sparse arithmetic computations. In addition, we prove that the integrated Design Space Exploration (DSE) engine achieves a 14.36x maximum speedup if compared to previous automated solutions in the literature.

Pairwise sequence alignment accounts for the majority of key genome analysis applications' runtime. Because of the quadratic time complexity of exact alignment algorithms, the community is moving away from exact algorithms in favor of heuristics that only compute high-quality results. However, the state of the art lacks hardware-accelerated versions of these heuristic algorithms as the vast majority of the available solutions still rely on implementing exact alignment algorithms. Moreover, hardware-based implementations lack high-level APIs that can simplify their integration in commonly used genomic pipelines, hindering their applicability in real-world scenarios. In this context, we present the first high-performance FPGA implementation of the popular X-drop heuristic alignment algorithm and provide an easy-to-use API for its integration. On a Xilinx Alveo U280, our FPGA design achieves up to 5× speed-up over SeqAn, the state-of-the-art software version of the algorithm, running on two Intel Xeon processors using 80 CPU threads. Moreover, our design is also 3.45× faster than ksw2, a state-of-the-art vectorized alignment algorithm that performs a similar heuristic to the one employed in the X-drop algorithm. Finally, our implementation also outperforms LOGAN, a recently published GPU implementation of X-drop running on an Nvidia Tesla V100, by a factor of 1.5×.

The intrinsic complexity of modern computing systems requires structured methods for analyzing and optimizing application performance. In this context, the Roofline model proposes an intuitive and visual method providing performance insight and optimization guidance for a given architecture. Although this methodology successfully models multicore and GPU performance optimizations, the original formulation does not directly apply to FPGA devices. For this reason, we propose a Roofline model analysis for reconfigurable architectures and an associated CAD tool for assisting HLS optimization of C/C++ applications. We firstly model FPGA attainable performance by means of an analytical method. Then, we integrate locality walls and a DSE engine for an enhanced optimization process. Starting from a software version of the N-body algorithm, we firstly illustrate how our methodology helps at quickly achieving performance comparable to a state-of-the-art FPGA bespoke implementation. Then, we illustrate an assisted platform porting of the Smith-Waterman sequence alignment providing a 9x speedup. Finally, we evaluated the single DSE engine on the Poly-Bench test suite and achieved performance improvements up to 14.36x compared to previous automated solutions in the literature.

The STEM field is characterized by a strong gender gap, both in Business and in Academia. Previous studies showed how the gender gap presents some peculiarities: women result to publish less than men across all disciplines, and this is the reason why this publication gap is often referred to as “productivity puzzle”. Strongly believing that gender should not influence the choice of the career to pursue, recent literature in organization has paid greater attention to gender related issues, analyzing the role played by team heterogeneity on performance. Such studies often obtained controversial outcomes, suggesting that the relationship between group heterogeneity and performance is a complex phenomenon. The dynamics taking place within working groups have been vastly studied in organizational psychology, showing that factors shaping group members' behavior are various. In this context, the working environment results to be a crucial factor. For these reasons, in this study we investigated the impact of heterogeneity on academic teams performance, taking into account gender representation in the overall working environment. More specifically, we evaluated the impact of diversity on the research conducted at the Dipartimento di Elettronica, Informazione e Biotecnologia of Politecnico di Milano, the first awarded technical university in Italy and at NECST Laboratory, a laboratory inside the Dipartimento di Elettronica, Informazione e Biotecnologia. Data are available for scientific paper published between 1965 and 2018. In this paper we studied the transformations occurred inside Dipartimento di Elettronica, Informazione e Biotecnologia in terms of gender representation between 1965 and 2018, taking into account teams characteristics, research outcomes and productivity puzzle. The results obtained showed how in both cases the impact of heterogeneity varied according to perceived value of diversity. Heterogeneity per se does not account for a boost in performance. Gender heterogeneity leads to an increase in performance only when also inclusion is achieved.

The acceleration of compute-intensive applications on FPGA-based systems has become an increasingly common trend thanks to their availability as cloud commodities. This trend has also been accompanied by wider support of High-Level Synthesis tools. Despite these solutions reduce the learning curve for hardware development, the programmer still requires specific expertise in order to achieve efficient implementations. In this paper, we propose an automated approach for the acceleration of C applications into dataflow kernels on FPGAs.

The growing interest in FPGA-based solutions for accelerating compute demanding algorithms is pushing the need for new tools and methods to improve productivity. In this work, we propose a methodology to support designers in generating optimal FPGA hardware implementations using High-Level Synthesis (HLS). First, we propose an automated roofline model generation that operates directly on a C/C++ description of the algorithm. The approach enables fast evaluation of the operational intensity of the target function and visualizes the main bottlenecks of the current HLS implementation, providing guidance on how to improve it. Second, we integrate it with a Design Space Exploration (DSE) methodology for quickly evaluating different HLS directives to identify an optimal implementation.

The 5-point relative pose problem is to identify the possible relative camera motions given five matching points from two calibrated views. Several algorithms for solving this problem have been presented in the literature providing different tradeoffs in terms of computational complexity and accuracy of the results. Indeed, the research in this field is driven mostly by the need for accurate solutions and high performance to cope with real-time requirements. In this work we propose an implementation to solve the 5-point relative pose problem accelerated on Field Programmable Gate Array (FPGA). The proposed architecture implements the classical Nister's algorithm as a deep pipeline deployed on a AWS F1 instance and outperforms software implementations by a factor ranging from 7.2X to 233X. Furthermore, it achieves a speedup of 64.2X compared to the Nister's software implementation with comparable accuracy.

The N-Body simulation process describes the evolution of a system of forces composed of N bodies, which may represent celestial objects, molecules, and so on. The most accurate algorithm for N-Body simulation, the All-Pairs method, is particularly compute intensive and software implementations on CPUs are inefficient in terms of performance and power consumption. An implementation on a hardware accelerator, such as an FPGA, would benefits in both these terms, exploiting a parallel execution at a relative low power profile. Moreover, it would also benefit faster methods with lower computational complexity, since many of them rely on the All-Pairs approach to approximate the calculation of forces. This work proposes a highly scalable, power efficient and high performance hardware architecture for the N-Body All-Pairs simulation problem. Our final implementation is able to scale up to systems with an arbitrary number of bodies thanks to a tiling approach that allows performance in the order of 13,441 MPairs/s, outperforming state of the art implementations on FPGA in terms of both pure performance, as well as performance per watt ratio. Finally, our design results to be more power efficient than Grape-8 ASIC.

The importance of High-Level Languages in abstracting machine language to enhance productivity has been proved in many sectors, and has recently encouraged the spread of reconfigurable hardware for general purpose computing. At the same time, Field Programmable Gate Arrays (FPGAs) become popular for data-intensive applications, because they promise customized hardware accelerators and achieve high-performance with low power consumption. However, taking advantage of parallel accesses to the local memories of FPGAs remains difficult, as it currently requires application re-engineering. A solution to this challenge is PolyMem, an easy-to-use parallel memory. In this work, we investigate the implementation, integration, and performance of PolyMem for HLS applications. To this end, we present a novel open-source implementation of PolyMem, optimized for the Xilinx Design Suite. We further demonstrate the use of PolyMem for three different case studies, implemented using both the Vivado workflow with a Virtex-7 VC707, and the SDx workflow with a Kintex Ultrascale 3 ADM-PCIE. Finally, we provide a thorough empirical analysis of these three cases studies in terms of latency, hardware resources, and productivity. Our results demonstrate that PolyMem delivers the expected performance, while enhancing productivity at the cost of a small increase in resources.

Since the end of Moore's law is limiting the growth of general purpose processors, High Performance Processing (HPC) systems are considering FPGA-based accelerators as a promising solution for several application fields. However, their employment poses challenges the research is still tackling, and existing tools and workflows do not naturally adapt to the scale and complexity of HPC domains. To help researchers and practitioners, this paper proposes CAOS, a platform that implements an FPGA development workflow tailored to HPC systems while being open to external contributions. Indeed, researchers and developers can plug into CAOS to experiment and compare their solutions at each step of the design flow. This paper describes the CAOS workflow and validates it against several case studies to assess its generality and highlight possible research contributions.

Stencil computations represent a highly recurrent class of algorithms in various high performance computing scenarios. The Streaming Stencil Time-step (SST) architecture is a recent implementation of stencil computations on Field Programmable Gate Array (FPGA). In this paper, we propose an automated framework for SST-based architectures capable of achieving the maximum performance level for a given FPGA device through 1) the maximization of basic modules instantiated in the design and 2) optimization of the design floorplanning. Experimental results show that the proposed approach reduces the design time up to 15× w.r.t. naive design space exploration approaches, and improves the performance of the 13%.

In the context of heterogneous computing, even though GPUs are the components of election due to both their intrinsically parallel nature and their flexibility, FPGAs are being investigated and experimented due to superior power efficiency on selected workloads While GPUs are the heterogeneous components of election due to both their intrinsically parallel nature and their flexibility, FPGAs are being investigated and experimented due to superior power efficiency on selected workloads. However, the lack of adequate languages, runtimes, programming flexibility and, broadly speaking, proven system level approaches for FPGA-accelerated applications are the most relevant limiting factors to the adoption of these devices into mainstream. In these regards, Amazon recently released Amazon Web Services (AWS) EC2 F1, which are compute instances that are equipped with Xilinx FPGA boards. On such instances, the user can develop algorithms and run them on FPGAs thanks to the new software developed by Xilinx called SDAccel. In this paper, we describe how we extended the CAOS framework to integrate with SDAccel and target AWS F1 instances for improving the performance of a custom application by means of FPGA acceleration. We then propose a case study to test the new methodology, based on the N-Body Simulation problem. Results show that we were able to achieve performance comparable to the ones obtained by expert users in less than a day of work.

When dealing with partially reconfigurable designs on field-programmable gate array, floorplanning represents a critical step that highly impacts system's performance and reconfiguration overhead. However, current vendor design tools still require the floorplan to be manually defined by the designer. Within this paper, we provide a novel floorplanning automation framework, integrated in the Xilinx tool chain, which is based on an explicit enumeration of the possible placements of each region. Moreover, we propose a genetic algorithm (GA), enhanced with a local search strategy, to automate the floorplanning activity on the defined direct problem representation. The proposed approach has been experimentally evaluated with a synthetic benchmark suite and real case studies. We compared the designed solution against both the state-of-the-art algorithms and alternative engines based on the same direct problem representation. Experimental results demonstrated the effectiveness of the proposed direct problem representation and the superiority of the defined GA engine with respect to the other approaches in terms of exploration time and identified solution.

Recent developments in Big Data frameworks are moving towards reservation based approaches as a mean to manage the increasingly complex mix of computations, whereas preemption techniques are employed to meet strict jobs deadlines. Within this work we propose and evaluate a new planning algorithm in the context of reservation based scheduling. Our approach is able to achieve high cluster utilization while minimizing the need for preemption that causes system overheads and planning mispredictions.

This work presents a novel floor planner tailored for Partially-Reconfigurable FPGAs having an arbitrary distribution of heterogeneous resources. The proposed approach precomputes a set of feasible placements for each of the reconfigurable regions, thus allowing the designer to set a preference on the types and positions of the desired areas. Then, the core of the approach is based on a Mixed-Integer Linear Programming (MILP) formulation which exploits constraints derived from a conflict graph to prevent overlapping between areas. Experimental results have shown that the defined approach leads to an average 11% improvements in the objective function value w.r.t. The state-of-the-art solutions under the same limited time budget.

The aim of this paper is to show a novel floorplanner based on Mixed-Integer Linear Programming (MILP), providing a suitable formulation that makes the problem tractable using state-of-the-art solvers. The proposed method takes into account an accurate description of heterogeneous resources and partially reconfigurable constraints of recent FPGAs. A global optimum can be found for small instances in a small amount of time. For large instances, with a time limited search, a 20% average improvement can be achieved over floorplanners based on simulated annealing. Our approach allows the designer to customize the objective function to be minimized, so that different weights can be assigned to a linear combination of metrics such as total wire length, aspect ratio and area occupancy.