As spiking-based deep learning inference applications are increasing in embedded systems, these systems tend to integrate neuromorphic accelerators such as µBrain to improve energy efficiency. We propose a µBrain-based scalable many-core neuromorphic hardware design to accelerate the computations of spiking deep convolutional neural networks (SDCNNs). To increase energy efficiency, cores are designed to be heterogeneous in terms of their neuron and synapse capacity (i.e., big vs. little cores), and they are interconnected using a parallel segmented bus interconnect, which leads to lower latency and energy compared to a traditional mesh-based Network-on-Chip (NoC). We propose a system software framework called SentryOS to map SDCNN inference applications to the proposed design. SentryOS consists of a compiler and a run-time manager. The compiler compiles an SDCNN application into sub-networks by exploiting the internal architecture of big and little µBrain cores. The run-time manager schedules these sub-networks onto cores and pipeline their execution to improve throughput. We evaluate the proposed big little many-core neuromorphic design and the system software framework with five commonly-used SDCNN inference applications and show that the proposed solution reduces energy (between 37% and 98%), reduces latency (between 9% and 25%), and increases application throughput (between 20% and 36%). We also show that SentryOS can be easily extended for other spiking neuromorphic accelerators such as Loihi and DYNAPs.

Computation-in-Memory (CIM) is an emerging computing paradigm to address memory bottleneck challenges in computer architecture. A CIM unit cannot fully replace a general-purpose processor. Still, it significantly reduces the amount of data transfer between a traditional memory unit and the processor by enriching the transferred information. Data transactions between processor and memory consist of memory access addresses and values. While the main focus in the field of in-memory computing is to apply computations on the content of the memory (values), the importance of CPU-CIM address transactions and calculations for generating the sequence of access addresses for data-dominated applications is generally overlooked. However, the amount of information transactions used for “address” can easily be even more than half of the total transferred bits in many applications. In this article, we propose a circuit to perform the in-memory Address Calculation Accelerator. Our simulation results showed that calculating address sequences inside the memory (instead of the CPU) can significantly reduce the CPU-CIM address transactions and therefore contribute to considerable energy saving, latency, and bus traffic. For a chosen application of guided image filtering, in-memory address calculation results in almost two orders of magnitude reduction in address transactions over the memory bus.

Heart activity can be monitored by means of ElectroCardioGram (ECG) measure which is widely used to detect heart diseases due to its non-invasive nature. Trained cardiologists can detect anomalies by visual inspecting recordings of the ECG signals. However, arrhythmias occur intermittently especially in early stages and therefore they can be missed in routine check recordings. We propose a hardware setup that enables the always-on monitoring of ECG signals into wearables. The system exploits a fully event-driven approach for carrying arrhythmia detection and classification employing a bio-inspired spiking neural network. The two staged Spiking Neural Network (SNN) topology comprises a recurrent network of spiking neurons whose output is classified by a cluster of Leaky integrate-and-fire (LIF) neurons that have been supervisely trained to distinguish 17 types of cardiac patterns. We introduce a method for compressing ECG signals into a stream of asynchronous digital events that are used to stimulate the recurrent SNN. Using ablative analysis, we demonstrate the impact of the recurrent SNN and we show an overall classification accuracy of 95% on the PhysioNet Arrhythmia Database provided by the Massachusetts Institute of Technology and Beth Israel Hospital (MIT/BIH). The proposed system has been implemented on an event-driven mixed-signal analog/digital neuromorphic processor. This work contributes to the realization of an energy-efficient, wearable, and accurate multi-class ECG classification system.

This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC). In particular, it presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is based on modeling at system level supported by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-Vtvoltage level as the digital logic. Reliability degradation is thus overcome and this opens the way to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to future 14 and 10 nm technology nodes.

Technology scaling enables the design of low cost biosignal processing chips suited for emerging wireless body-area sensing applications. Energy consumption severely limits such applications and memories are becoming the energy bottleneck to achieve ultra-low-power operation. When aggressive voltage scaling is used, memory operation becomes unreliable due to the lack of sufficient Static Noise Margin. This paper introduces an approximate biosignal Compressed Sensing approach. We propose a digital architecture featuring a hybrid memory (6T-SRAM/SCMEM cells) designed to control perturbations on specific data structures. Combined with a statistically robust reconstruction algorithm, the system tolerates memory errors and achieves significant energy savings with low area overhead.

In order to provide better services to elderly people, home healthcare monitoring systems have been increasingly deployed. Typically, these systems are based on wireless sensor nodes, and should utilize very low energy during their lifetimes, as they are powered by scavengers. In this article, we present an ultra-low power processing system for a wireless sensor node for very low duty cycle applications. In the CoolBio system-on-chip, we utilized several power reduction techniques at both the architecture level and the circuit level. These techniques include feature extraction, voltage and frequency scaling, clock and power gating and a redesign of key standard cells. In the design of the ultra-low power processing system, we paid special attention to the memory subsystem, as it is one of the most power-consuming modules in a design. We also designed a clock manager in order to reduce the power consumed by clocking, and a power manager that is able to power-off unutilized modules. The proposed wireless sensor node processing system consumes 36.4μW at 100MHz and 1.2V supply voltage, for a heartbeat-detection algorithm with a 0.01% duty cycle.