This article presents an integrated independently programmable multioutput (MO) successive approximation (SAR) switched-capacitor (SC) DC-DC converter with two independently programmable output channels ranging outputs between 0.4 V and$V_{\text {BAT}}$with resolution of$V_{\text {BAT}}/{3^{N}}$where$V_{\text {BAT}}$is the input voltage and N is the number of SC units cascaded in SAR structure. A modified dual-output (DO) SC DC-DC converter unit cell is proposed with reduced ripple at its output and is integrated in the SAR-SC structure to deliver a wide input and output voltage range. The modified DO-SC units are cascaded via switch boxes to yield a fine-grain voltage resolution. The 1357 ordered pairs of conversion ratios (CRs) ensure that the two output channels are orthogonal and have near-zero crosstalk under varying load conditions. The proposed converter is fabricated in 180 nm CMOS process and achieves a peak efficiency of 94% across a combined load variation of 10 to$800{\,}\mu $A.

Multibit (MB) quantization allows high resolution Delta-Sigma modulators (DSMs) with low oversampling ratio (OSR). Furthermore, it allows higher maximum stable amplitude (MSA), achieves reduced jitter sensitivity, and relaxes the dynamic requirements on the DSM loop-filter (LF). However, MB quantization adds a dominant source of non-linearity due to element mismatch in the MB digital-to-analog converter (DAC) which often dominates the performance. State of the art (SoA) presents many calibration techniques, though digital power and area consumption can be high and calibration time be significant. In this paper we target a calibration-free DAC based on dual quantization and propose to employ a Multistage noise SHaping (MASH) Digital-DSM (DDSM) to avoid architectural compromises between the main DSM LF and the DDSM DAC. The implementation trade-offs are illustrated, and stability constraints in both the main LF and the DDSM are addressed. An exemplary implementation is derived and simulated, and the results shall lay the foundation for future circuit implementations of MASH DDSM to realize MB DSM with intrinsically high linearity.

Triboelectric generators (TEGs) are effective kinetic energy transducers with time-varying internal capacitances, posing challenges for efficient energy extraction. This work presents an integrated interface circuitry for triboelectric generators (TEGs) where rectification and regulation are combined in a single stage which minimizes the number of charge transfer stages and power losses in the front-end diode bridge rectifiers and thus results in improved efficiency. The proposed circuit also addresses the issue of the asymmetric TEG output during the positive and negative half-cycles. It performs active rectification of the low amplitude alternating current output generated during the negative half-cycle, corresponding to the release cycle of the device. The proposed circuit is designed and fabricated using 180nm CMOS BCD process. The experimental characterization of the fabricated integrated circuit (IC) is conducted by interfacing it with in-house fabricated TEG device. The developed harvesting system demonstrates an energy conversion efficiency of 75.6%. Overall, the proposed single-stage interface circuit presents a compelling alternative to the conventional two-stage interfacing approach in terms of simplicity, reliability, robustness and potentially lowered costs and power consumption. Additionally, the system supports cold start-up without an external power supply.

The design automation of analog circuits poses significant challenges in terms of the large design space, complex interdependencies between circuit specifications, and resource-intensive simulations. To address these challenges, this paper presents an innovative framework called the Graph of Circuits Explorer (GCX). Leveraging graph structure learning along with graph neural networks, GCX enables the creation of a surrogate model that facilitates efficient exploration of the optimal design space within a semi-supervised learning framework which reduces the need for large labelled datasets. The proposed approach comprises three key stages. First, we learn the geometric representation of circuits and enrich it with technology information to create a comprehensive feature vector. Subsequently, integrating feature-based graph learning with few-shot and zero-shot learning enhances the generalizability in predictions for unseen circuits. Finally, we introduce two algorithms namely, EASCO and ASTROG which upon integration with GCX optimize the available samples to yield the optimal circuit configuration meeting the designer's criteria. The effectiveness of the proposed approach is demonstrated through simulated performance evaluation of various circuits, using derived parameters in 180nm CMOS technology. Furthermore, the generalizability of the approach is extended to higher-order topologies and different technology nodes such as 65nm and 45nm CMOS process nodes.

This work presents the system level modelling of a hybrid energy harvesting device incorporating piezoelectric and electromagnetic transducers in order to optimize its output performance. The coupled electromechanical analysis of the device dynamics shows that the strong impedance mismatch between piezoelectric and electromagnetic components restricts the potential of the hybrid generator which can only be improved through innovation in the power management circuit. We propose a novel interface circuit topology, which uses synchronous electric charge extraction technique to combine the extracted energy from piezoelectric and electromagnetic harvesters. The designed circuits are simulated for CMOS 180 nm process and the peak improvement obtained using the proposed technique is more than 1.3 times of the combined power when harvested individually.

Dual quantization is an effective method to combine the benefit of single bit quantization, which results in inherently linearized DAC, and multibit quantization, which results in lower sampling rate. However, extra noise inserted in the loop due to requantization needs to be shaped out of the signal band to ensure the inband characteristics to remain as without the dual quantization. However, this additional shaping may result in extra noise injected into out of the band, which, if not filtered properly, may affect the loop dynamics and stability. Prior arts have used FIR filtering to filter out this additional digital quantization noise but in an ineffective way. In this paper, we show that the cutoff of the FIR filter can be reduced to much lower than Nyquist bandwidth(fs/2) and can be brought close to the signal bandwidth of the modulator resulting in a further improved performance.

The jitter sensitivity of continuous-time ΣΔ modulators is well known. It becomes an even more severe performance bottleneck in receiver applications, when out-of-band interferers are present together with colored phase noise. Bandpass ΣΔ modulators, as a competitive candidate for software-defined radios, are typically considered to be disadvantageous regarding jitter, and it can be shown that they are at least similarly affected by jitter as the mixer in a direct conversion receiver. In this paper, an analog interferer suppression technique is presented for bandpass ΣΔ modulators, which allows them to be more tolerant to interferer induced jitter error, thereby relaxing the overall clock phase noise requirements compared to other receiver architectures. The proposed technique is also combined with a previously published digital interferer suppression technique in order to provide suppression over a larger frequency range.

Time interleaving is one of the prominent ways to increase the operating speed of data converters. However, mis-match artifacts among the time interleaving sections impair the performance benefits obtained from the use of time interleaving. CTDSMs with time interleaved quantizers are particularly affected by the gain mismatch in the time interleaved feedback DAC. We present a circuit technique to eliminate this adverse effect of the gain mismatch between time interleaved sections in 2×-time interleaved quantizers. The proposed technique involves the use of a three state DAC as a feedback DAC element. The simulations results obtained from the schematic level implementation of the proposed three state DAC in 40nm CMOS process demonstrate the efficacy of the presented idea.

A delta-sigma modulator architecture reducing the impact of the digital-to-analog converter (DAC) non-linearity in a multi-bit delta-sigma DAC is presented. By cascading and deterministic dithering, only small signals are processed by the multi-bit DAC, thus a large dynamic range can be maintained; by suppressing the out-of-band noise before being processed by the multi-bit DAC, less shaped-noise gets inter-modulated by the non-linear DAC, thus the raise of noise floor is reduced. The proposed architecture provides a practical way to implement a high-resolution multi-bit delta-sigma DAC at low over-sampling rate (OSR). System level simulations in MATLAB show that an average ENOB=14.5-bits can be achieved with 0.2% (standard deviation) DAC element mismatch at OSR = 10.

Characterizing wide band continuous-time ΔΣ modulators is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. Experimental results from a single-bit CTDSM operating at 4.4 GHz are given, demonstrating the efficacy of the technique.