EDBT 2026 Demo / reviewers in the wild / expert
Ting-Ju Chen
dblp:16/10356
· DBLP profile ↗
4ranked-venue papers
2as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 1 since 2021Human-computer interaction and ubiquitous computing · 2 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer graphics and multimedia
1 paper |
Geometric modeling and processing · 50% Image and video processing · 50% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 80% Memory systems · 20% | |
| Artificial intelligence
1 paper |
Representation and self-supervised learning · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Image and video processing › video frame interpolation › interpolation
image interpolation |
0.5 | 1 | 2021 | Latent Embedded Graphs for Image and Shape Interpolation · Comput. Aided Des. 2021 |
Geometric modeling and processing › shape deformation
shape interpolation |
0.5 | 1 | 2021 | Latent Embedded Graphs for Image and Shape Interpolation · Comput. Aided Des. 2021 |
Machine learning › Representation and self-supervised learning
latent space representation |
0.1 | 1 | 2021 | Latent Embedded Graphs for Image and Shape Interpolation · Comput. Aided Des. 2021 |
Hardware reliability and fault tolerance › memory reliability
built-in redundancy analysis |
0.1 | 1 | 2012 | Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Hardware reliability and fault tolerance › memory repair
built-in self-repair |
0.1 | 1 | 2012 | Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Hardware reliability and fault tolerance
memory repair |
0.1 | 1 | 2012 | Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Memory systems
random-access memory |
0.1 | 1 | 2012 | Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Hardware reliability and fault tolerance › redundancy
redundancy analysis |
0.1 | 1 | 2012 | Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Methods — techniques the papers use, named apart from their topics
redundancy allocation · 0.1reconfigurable BIRA · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Latent Embedded Graphs for Image and Shape Interpolation
Shantanu Vyas, Ting-Ju Chen, Ronak R. Mohanty, Peng Jiang 0019, Vinayak R. Krishnamurthy |
Comput. Aided Des. | 2 |
| 2020 | QCue: Queries and Cues for Computer-Facilitated Mind-MappingabstractWe introduce a novel workflow, QCue, for providing textual stimulation during mind-mapping. Mind-mapping is a powerful tool whose intent is to allow one to externalize ideas and their relationships surrounding a central problem. The key challenge in mind-mapping is the difficulty in balancing the exploration of different aspects of the problem (breadth) with a detailed exploration of each of those aspects (depth). Our idea behind QCue is based on two mechanisms: (1) computer-generated automatic cues to stimulate the user to explore the breadth of topics based on the temporal and topological evolution of a mind-map and (2) user-elicited queries for helping the user explore the depth for a given topic. We present a two-phase study wherein the first phase provided insights that led to the development of our work-flow for stimulating the user through cues and queries. In the second phase, we present a between-subjects evaluation comparing QCue with a digital mind-mapping work-flow without computer intervention. Finally, we present an expert rater evaluation of the mind-maps created by users in conjunction with user feedback. Ting-Ju Chen, Sai Ganesh Subramanian, Vinayak R. Krishnamurthy |
Graphics Interface | 1 |
| 2018 | To Draw or Not to Draw: Recognizing Stroke-Hover Intent in Non-instrumented Gesture-free Mid-Air SketchingabstractDrawing curves in mid-air with fingers is a fundamental task with applications to 3D sketching, geometric modeling, handwriting recognition, and authentication. Mid-air curve input is most commonly accomplished through explicit user input; akin to click-and-drag, the user may use a hand posture (e.g. pinch) or a button-press on an instrumented controller to express the intention to start and stop sketching. In this paper, we present a novel approach to recognize the user's intention to draw or not to draw in a mid-air sketching task without the use of postures or controllers. For every new point recorded in the user's finger trajectory, the idea is to simply classify this point as either hover or stroke. Our work is motivated by a behavioral study that demonstrates the need for such an approach due to the lack of robustness and intuitiveness while using hand postures and instrumented devices. We captured sketch data from users using a haptics device and trained multiple binary classifiers using feature vectors based on the local geometric and motion profile of the trajectory. We present a systematic comparison of these classifiers and discuss the advantages of our approach to spatial curve input applications. Umema Bohari, Ting-Ju Chen, Vinayak R. Krishnamurthy |
IUI | 2 |
| 2012 | Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMsabstractBuilt-in self-repair (BISR) techniques are widely used for the repair of embedded memories. One of the key components of a BISR circuit is the built-in redundancy-analysis (BIRA) module, which allocates redundancies according to the designed redundancy analysis algorithm. Thus, the BIRA module affects the repair rate of the BISR circuit. Existing BIRA schemes for RAMs can provide the optimal repair rate (the ratio of the number of repaired RAMs to the number of defective RAMs), but they require either high area cost or multiple test runs. This paper proposes a BIRA scheme for RAMs, which can provide the optimal repair rate using very low area cost and single test run. Furthermore, the BIRA is designed as reconfigurable such that it can be shared by multiple RAMs. Experimental results show that the area cost for implementing the proposed BIRA scheme is much lower than that of existing BIRA schemes with optimal repair rate. A test chip is also implemented to demonstrate the proposed BIRA scheme. Ting-Ju Chen, Jin-Fu Li 0001, Tsu-Wei Tseng |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |