Hardware invariants are known to facilitate bit-flip detection during post-silicon validation. In this paper, we present a fully automated SAT-based methodology for fast generation of hardware invariants by using the built-in pruning mechanisms within SAT solvers, namely learned clauses. These candidates are evaluated for their potential to detect bit-flips using a new incremental SAT-based approach. In addition to speeding-up the simulation-based approaches for invariant generation and evaluation, when compared to the known art, our results show improvements in both the number of flip-flops that can be covered for bit-flip detection, as well as for the on-chip area for the bit-flip detection unit.

The objective of post-silicon validation is to identify design errors that remain undetected after pre-silicon verification and, therefore, manifest themselves in the silicon prototypes. These errors are often associated with the subtle interactions between the electrical states of the systems and commonly manifest in the logic domain as bit-flips in flip-flops. They occur under unique operating conditions, which are often not-easily repeatable. In order to shorten the long detection latencies from an error's occurrence until its observation (i.e., system crash), embedded assertion checkers can be employed. Nonetheless, relying on simulation-based experiments for selecting and assessing the practical effectiveness of a subset of assertion checkers (to be implemented in the physical device) suffers from the slow simulation speed. To address this concern, in this paper, we present a systematic methodology to automatically design emulation-based experiments that can aid the selection and assessment of the embedded assertion checkers. Our results indicate improvements of up to 10% on average for the coverage of flip-flops that are affected by bit-flips when compared with results obtained by simulation-based experiments.

Post-silicon validation deals with detection and diagnosis of errors that, due to existing limitations in pre-silicon verification, escape to the silicon prototypes and need to be fixed before committing to high-volume manufacturing. Electrical errors, such as those caused by cross-talk or power droops, are particularly difficult to catch during the pre-silicon phase because of the insufficient accuracy of device models, which is often traded-off against simulation time. This challenge is further aggravated by the rising number of voltage domains, especially if subtle errors are excited in unique electrical states. In fact these electrically-induced subtle errors most commonly manifest in the logic domain as bit-flips and, to the best of our knowledge, there are no systematic methods for designing embedded hardware monitors for generic logic blocks that can detect bit-flips with low detection latency. Moreover, unlike pre-silicon verification and manufacturing test that benefit from well-defined and universally accepted coverage metrics, there is no generic metric from which confidence can be implied at the end of post-silicon validation. Toward these goals, we present a method that relies on design invariants (assertions) that are ranked based on their potential to detect bit-flips. We also introduce two metrics bit-flip coverage estimate and flip-flop coverage estimate that can be used to assess the quality of the selected assertions, and, in general, the effectiveness of the post-silicon validation process.

The objective of post-silicon validation is to detect design errors on early silicon prototypes. Electrically-induced errors commonly manifest as bit-flips in the logic domain and they occur under unique operating conditions, which are often not-easily-repeatable. In order to shorten the long detection latencies from an error's manifestation until its observation (i.e. system crash), embedded assertion checkers can be employed. Nonetheless, relying on simulation-based experiments for selecting and assessing the usefulness of a subset of assertion checkers (to be committed to silicon) suffers from limitations associated with the slow simulation speed. To address this concern, in this paper we present a systematic method to automatically design emulation-based experiments that can aid the selection and assessment of the embedded assertion checkers. Our results indicate improvements of up to 10% on average for the coverage of flip-flops that are affected by bit-flips when compared to results obtained from simulation-based experiments.

A novel approach is proposed for analogue circuits that identifies which devices should be replaced with configurable analogue transistors (CATs) to maximise post fabrication yield. Both performance sensitivity and adjustment independence are considered when identifying these critical devices, giving a combined weighted sensitivity. The results from an operational amplifier case study are presented where it is demonstrated that variation in key circuit performances can be reduced by an average of 78.8% with the use of only three CATs. These results confirm that the proposed critical device selection method with optimal performance driven CAT sizing can lead to significant improvement in overall performance and yield.